Intel 21555 manual Asynchronous Clocking, Optional Configurations

Optional Configurations

•In the other configuration, the central function is controlled by the intelligent subsystem through the J1 connector.

Table 12. External Arbiter Switch Option

Switch	Switch	Switch Down	Switch Up	Description
Pack
J20	SW5	Enable the 21555	System slot (J102) as	Central Function Mode(pr_ad<6>)
		as central arbiter	Central Function
J21	SW1	Disable the 21555	System slot (J102) as	Disable 21555 arbiter.
		as central arbiter	external arbiter.

Table 13 shows how the req# and gnt # lines must be configured for PICMG operation.

Table 13. J21 Switch Operations for Central Function and Arbiter Control

Switch	Switch	Request/	Switch Down	Switch Up
Pack		Grant	System slot (J102) as arbiter	21555 as arbiter
	SW2	req#0	PICMG GNT becomes slot grant	req=req
J21	SW3	gnt#0	PICMG REQ becomes slot grant	gnt=gnt
	SW4	req#1	REQ1 from PICMG slot	REQ1 from drawbridge
	SW5	gnt#1	GNT1 from PICMG slot	GNT1 from drawbridge

3.3Asynchronous Clocking

Table 14 shows how to configure the J20 switches for synchronous or asynchronous operations of the local bus. If the PICMG slot is the source of the clocks, the resistor strapping options must be followed as described in Section 3.1. In addition, J20 SW3 must be set for asynchronous clocking and s_clk_o needs to be disabled from the 21555.

Table 14. Switch Operations for Synchronous or Asynchronous Clock Control

Switch	Switch	Switch Down	Switch Up	Description
Pack
		Synchronous host and	Asynchronous host and	Selects synchronous or
	SW3			asynchronous operation.
		local clock domains	local clock domains
				(pr_ad<4>)
J20
	SW4	Disable 21555 (s_clk_o)	Enable 21555 (s_clk_o)	s_clk_o
				(pr_ad<5>)

22 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide