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Intel 21555 manual Signal and Default Information, Table A-2. J4 Pin Assignments

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Signal and Default Information

Table A-2gives the Mictor connectors pin assignment and DE1B55503 schematic signal names.

Table A-2. J4 Pin Assignments

Schematic	Mictor		Mictor	Schematic
Signal Name	Pin Number		Pin Number	Signal Name

+5V	1		2	SCL

GND	3		4	SDA

S_CLK0_2	5		6	S_CLK0_3
CLK	5		6	CLKB
CLK				CLKB

S_AD31	7		8	S_AD15

S_AD30	9		10	S_AD14

S_AD29	11		12	S_AD13

S_AD28	13		14	S_AD12

S_AD27	15		16	S_AD11

S_AD26	17		18	S_AD10

S_AD25	19		20	S_AD9

S_AD24	21		22	S_AD8

S_AD23	23		24	S_AD7

S_AD22	25		26	S_AD6

S_AD21	27		28	S_AD5

S_AD20	29		30	S_AD4

S_AD19	31		32	S_AD3

S_AD18	33		34	S_AD2

S_AD17	35		36	S_AD1

S_AD16	37		38	S_AD0

Table A-3gives the Mictor connectors pin assignment and DE1B55503 schematic signal names.

Table A-3. J5 CBE, REQ, and GNT

Schematic			Mictor		Mictor	Schematic
Signal Name			Pin Number		Pin Number	Signal Name

	+5V		1		2		SCL

	GND		3		4		SDA

S_CLK0_2			5		6	S_CLK0_3
	CLK		5		6		CLKB
	CLK						CLKB

			7		8
	S_CBE7		7		8		S_REQ0


	S_CBE6		9		10		S_GNT8


	S_CBE5		11		12		S_GNT7


	S_CBE4		13		14		S_GNT6


	S_CBE3		15		16		S_GNT5


	S_CBE2		17		18		S_GNT4


	S_CBE1		19		20		S_GNT3


	S_CBE0		21		22		S_GNT2

24	21555 PCI-to-PCI Bridge Evaluation Board User’s Guide

Image 24

Intel 21555 manual Signal and Default Information, Table A-2. J4 Pin Assignments, Table A-3. J5 CBE, REQ, and GNT

Contents

User’s Guide 21555 PCI-to-PCI Bridge Evaluation BoardNovember 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Contents FiguresTables J21 Switch Operations for Central Function and Arbiter ControlSwitch Operations for Synchronous or Asynchronous Clock Control 1.2 Features Introduction1.1 Overview 1.3.1 Connectors 1.3 Major ComponentsIntroduction 1.3.2 Switches and Jumper 1.3.3 DevicesIntroduction 1.4 Switch Settings Figure 2. SwitchesIntroduction 1.5 Stake-Pin Jumper Table 1. DIP Switch OperationIntroduction Table 2. Stake-Pin Jumper a1.6 Resistor Jumpers 21555Introduction Figure 3. Jumper Resistors1.6.1 Clock Configuration 1.6.2 Clamping VoltageTable 3. Clock Configuration Jumpers Introduction1.7 Secondary Slot Numbering and IDSEL Mapping IntroductionFigure 4. Local PCI Slot Numbering Table 5. Slot and IDSEL Mapping1.8 Interrupt Routing IntroductionTable 6. Interrupt ORing 1.9 Typical Configurations Introduction21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 21555Introduction Figure 6 shows the DE1B55503 with two local bus option cardsFigure 6. DE1B55503 with Two Local Bus Option Cards 21555 PCI-to-PCI Bridge Evaluation Board User’s GuidePage Operations and Installation 2.2 Hardware Requirements2.3 Software Requirements 2.1 SpecificationsOperations and Installation 2.3.1 Programming the SROM2.3.2 Programming the Flash ROM 2.4 Installation Procedure 2.3.2.1 Board SetupOperations and Installation 2.3.2.2 Running DbFlash.exe2.5 Interrupt Routing Operations and InstallationTable 9. Interrupt ORing Optional Configurations 3.1 PICMG Configuration3.2 Central Function and Arbiter Control Optional Configurations 3.3 Asynchronous ClockingSignal and Default Information A.1 J2 J4, J5, and J6 Connector Pinouts21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Signal and Default Information Table A-2. J4 Pin AssignmentsTable A-3. J5 CBE, REQ, and GNT Signal and Default Information 21555 PCI-to-PCI Bridge Evaluation Board User’s GuideLSTAT A.2 JATAG Connector Pinout A.3 Factory Default Switch and Jumper ConfigurationSignal and Default Information Table A-5. J1 JATAG Connector