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Intel 21555 manual Interrupt Routing, Operations and Installation, Interrupt ORing

Models: 21555

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Operations and Installation

connectors and one (1) connector-less slot. Section 1.9, “Typical Configurations” on page 14 shows examples of typical PCI configurations.

6.Apply power to the system.

7.Verify the auto-configuration of the 21555 and other options.

a.If the on-board ROM is preloaded the 21555 banner displays.

b.Verify that system BIOS or firmware detects and configures the 21555.

c.To verify the loading of the SROM, run the MKSROM utility without an SROM file as an input. See Section 2.3.1, “Programming the SROM” on page 18.

8.PCI bus data, address, and control signals are monitored by connecting a logic analyzer to Mictor connectors J2, J4, J5, and J6. See Appendix A, “Signal and Default Information”

2.5Interrupt Routing

Table 9 shows the ORing of interrupts. A total of 12 interrupts are connected to each of three secondary bus PCI slots but four interrupts are driven to the card edge. The 12 incoming interrupts must be combined. Interrupt ORing is in accordance with the PCI-to-PCI Bridge Architecture Specification V2.x.

In accordance with the PCI Bridge Architecture Specification, the interrupts of the devices on the secondary slots are wire ORed and routed to PCI fingers of the DE1B55503.

Table 9. Interrupt ORing

	Device Number	Interrupt Pin on	Interrupt Pin on Board
	Device Number	Device	Connector
		Device	Connector

		INTA#	INTB#
	5	INTB#	INTC#
	(Optional Slot J101)	INTC#	INTD#
		INTD#	INTA#

		INTA#	INTA#
	6	INTB#	INTB#
	(PICMG slot J101)	INTC#	INTC#
		INTD#	INTD#

		INTA#	INTD#
	7	INTB#	INTA#
	(Top slot J7)	INTC#	INTB#
		INTD#	INTC#

20	21555 PCI-to-PCI Bridge Evaluation Board User’s Guide

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Intel 21555 manual Interrupt Routing, Operations and Installation, Interrupt ORing

Contents

November User’s Guide21555 PCI-to-PCI Bridge Evaluation Board 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Contents FiguresSwitch Operations for Synchronous or Asynchronous Clock Control TablesJ21 Switch Operations for Central Function and Arbiter Control 1.1 Overview 1.2 FeaturesIntroduction Introduction 1.3.1 Connectors1.3 Major Components Introduction 1.3.2 Switches and Jumper1.3.3 Devices Introduction 1.4 Switch SettingsFigure 2. Switches 1.5 Stake-Pin Jumper Table 1. DIP Switch OperationIntroduction Table 2. Stake-Pin Jumper a1.6 Resistor Jumpers 21555Introduction Figure 3. Jumper Resistors1.6.1 Clock Configuration 1.6.2 Clamping VoltageTable 3. Clock Configuration Jumpers Introduction1.7 Secondary Slot Numbering and IDSEL Mapping IntroductionFigure 4. Local PCI Slot Numbering Table 5. Slot and IDSEL MappingTable 6. Interrupt ORing 1.8 Interrupt RoutingIntroduction 1.9 Typical Configurations Introduction21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 21555Introduction Figure 6 shows the DE1B55503 with two local bus option cardsFigure 6. DE1B55503 with Two Local Bus Option Cards 21555 PCI-to-PCI Bridge Evaluation Board User’s GuidePage Operations and Installation 2.2 Hardware Requirements2.3 Software Requirements 2.1 Specifications2.3.2 Programming the Flash ROM Operations and Installation2.3.1 Programming the SROM 2.4 Installation Procedure 2.3.2.1 Board SetupOperations and Installation 2.3.2.2 Running DbFlash.exeTable 9. Interrupt ORing 2.5 Interrupt RoutingOperations and Installation 3.2 Central Function and Arbiter Control Optional Configurations3.1 PICMG Configuration Optional Configurations 3.3 Asynchronous Clocking21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Signal and Default InformationA.1 J2 J4, J5, and J6 Connector Pinouts Table A-3. J5 CBE, REQ, and GNT Signal and Default InformationTable A-2. J4 Pin Assignments LSTAT Signal and Default Information21555 PCI-to-PCI Bridge Evaluation Board User’s Guide A.2 JATAG Connector Pinout A.3 Factory Default Switch and Jumper ConfigurationSignal and Default Information Table A-5. J1 JATAG Connector