1.4.2AT Escape Sequences, 1.4.3Dial Modifier | Intel 536EX specs

1.4.2AT Escape Sequences

Introduction

1.4.2AT Escape Sequences

The 536EX provides the industry-standard escape sequence, TIES (Time Independent Escape Sequence). TIES is designed to work with existing communication software written for the Hayes Escape Sequence.

Upon special request, Ambient provides the Hayes* Escape Sequence; however, please note that licensing can be required.

TIES/Hayes* Escape Sequences

The 536EX modem chipset is manufactured with TIES (Time Independent Escape Sequence) as the default setting. It is Hayes’ position that you must have a valid license from Hayes Micro Computer of Norcross, Georgia, before producing modem systems that use the Hayes Escape Sequence.

Intel accepts no responsibility and does not indemnify nor in any way provide protection for patent or possible patent violations to its customers or users of it products.

1.4.3Dial Modifier

Command	Function

0 to 9	Dialing digits

A, B, C, D, *, #	Tone dial characters

P	Pulse dial

R	Reverse Originate mode

S=n	Dial NVRAM telephone number

T	Tone dial

W	Wait for dial tone

,	Pause

!	Flash hook

@	Wait for quiet answer

;	Return to command state

- ( )	Ignored by modem

536EX Chipset Developer’s Manual

13

Intel Confidential

Image 13

Intel 536EX manual 1.4.2AT Escape Sequences, 1.4.3Dial Modifier, Intel Confidential, Introduction

Contents

Developer’s Manual 536EX ChipsetJanuary 536EX Chipset Developer’s Manual Intel Confidential Contents Contents Figures Tables Date Revision HistoryRevision Description 1.1Controllerless Modem Driver Overview Introduction 1.1.2Windows 95 and Windows Figure 1. WDM Driver Block DiagramUser applications Kernel - ring0 1.2V.90/V.92 and V.34 Data Modes Figure 2. VxD Mini Port Driver Block Diagram 1.3Modem Connection Overview Table 2. DCE-to-DCEData Rates for Each Mode Table 1. DTE-to-DCEData Rates for Each ModeTable 3. DCE-to-ISPData Rates for V.90 Mode Table 4. DTE-ModemData Rate Response Codes 1.4.1Sending Commands 1.4.3Dial Modifier 1.4.2AT Escape Sequences AT Command Summary Tables AT Command Summary TablesTable 5. Data Mode Command Summary Table 5. Data Mode Command Summary Continued Result code type Table 5. Data Mode Command Summary Continued Generate data mode calling tone Table 6. V.44/V.42/V.42 bis MNP Command Summary Intel Confidential Table 8. Fax Class 1 Command Summary Table 7. Fax Identity Command Summary Table 10. Voice DTE→DCE Character Pairs Table 9. IS-101Voice Command Summary Table 11. Voice DTE←DCE Character Pairs Table 10. Voice DTE→DCE Character Pairs Continued Table 12. Dial Modifiers Table 11. Voice DTE←DCE Character Pairs ContinuedTable 13. S-RegisterSummary Table 13. S-RegisterSummary Continued Data Mode AT COMMANDS Data Mode AT COMMANDS Figure 3. Example of a Remote Connection Table 14. Data Reporting Wn MappingATW0 •ATW2 Intel Confidential +FMFR?, +FMDL?, +FREV? 3.7Hanging Up Hn, S10, Zn, &D2 3.6Online Command Mode Escape Codes, On3.8Modem-to-ModemConnection Data Rates Intel Confidential +PCW=0 +PMH=0+VCID=1 +++AT Intel Confidential hook to connect the call. Now you can answer the phone and talk. After completing your voice conversation, the modem will issue another +PMHF and ATO command to initiate a Quick Connect. If the server rejects the request to go on hold, the user can stay on line ATO command issued or disconnect from his initial data connection ATH command issued Table 16. Supported Modulation Types 3.9.1Local Analog Loopback AT&T1 3.9Diagnostic Testing S18, &Tn LOCAL MODEM 3.9.2Local Analog Loopback With Self-TestAT&T8Figure 6. Local Analog Loopback Test Local Modem or Test Modem Licensing Requirements for Hayes Escape Sequence 3.10.1Time-IndependentEscape Sequence Format <char1><char2><char3><AT command><contents of S3>char1 = char2 = char3 = escape character S2 3.10.2Hayes* Escape Sequence Table 18. Data Mode Command Descriptions Intel Confidential Sn=x Intel Confidential Data Mode AT COMMANDS536EX Chipset Developer’s Manual NOTE: An asterisk * denotes the factory-defaultsetting AT&V0 Intel Confidential Indication Command DefaultDefinition 1, 0, Intel Confidential +ETBM +ESR1, 1, +GSN +GMR+IFC +ILRR=m Intel Confidential Description <carrier>+MS=m see ‘m’ +PMHF +PHSW=<value> +PMHR Intel Confidential Error Correction and Data Compression Error Correction and Data Compression4Table 19. Operating Modes NOTES Table 20. Resulting +ES Connection Types Intel Confidential Error Correction and Data Compression536EX Chipset Developer’s Manual Intel Confidential direction +DR=m+DS=m <max string> +EFCS=m 3768 +ER=m +ES=m 5.1Fax Identity Commands Fax Class 1 AT Commands5.2Fax Class 1 Commands Fax Class 1 AT Commands Table 23. <mod> Selection Table Figure 8. T.30 HDLC Frame Format Table 24. Fax Mode Command Descriptions +FRH=m Table 24. Fax Mode Command Descriptions ContinuedRefer to Table 23 on page shown in Table 23 on page +FTH=m IS-101Voice Mode AT Commands IS-101Voice Mode AT Commands 6.1DTMF Detection Reporting Table 25. Voice Mode Command Descriptions6.2Relay Control m = <deassert>, <assert> +FLO=m +VDR=m m=<enable>, <report> +VEM=m m = <mask> Intel Confidential +VIP +VLS=m Preassigned Voice I/O Labels Relay/Playback Control: cont Voice I/O Primitive Codes m = <sds>, <sdi> +VRX+VSD=m +VSM=m m= <cml>, <vsr>, <scs>, <sel>Transmission: Range: +VSP=m Compression Method Selection: cont factory default is ‘0’ none +VTS=m Default CommandDescription DTMF and Tone Generation: cont Table 26. S-RegisterCommand Descriptions S-RegistersS-Registers S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Caller ID Caller IDTable 27. Caller ID Tags for Formatted Reporting RING RING RING DATE = TIME = NMBR = NAME = DOE JOHN MESG =<DLE> R NMBR = UART Parallel Host Interface 16C450/16C550AParallel Host Interface 16C450/16C550A UART Figure 11. UART Emulation in Intelsdb.VxD UART Receiver Flow Diagram UART Transmitter Flow Diagram BIT NUMBER REGISTERADDRESS NAME 9.2.2Modem Status Register MSR 9.2.1Scratch Register SCRFigure 14. Scratch Register SCR Figure 15. Modem Status Register MSR Figure 16. Line Status Register LSR 9.2.3Line Status Register LSR 9.2.5Line Control Register LCR 9.2.4Modem Control Register MCRFigure 17. Modem Control Register MCR Figure 18. Line Control Register LCR Register 9.2.6FIFO Control Register FCRFigure 19. FIFO Control Register FCR Figure 20. Interrupt Identity Register IIR 9.2.7Interrupt Identity Register IIRTable 28. Interrupt Control Functions Figure 21. Interrupt Enable Register IER 9.2.8Interrupt Enable Register IER9.2.9Transmitter Holding Register THR Figure 22. Transmitter Holding Register THR 9.2.11Divisor Latch Registers DLM and DLL 9.2.10Receiver Buffer Register RBRFigure 23. Receiver Buffer Register RBR Figure 24. Divisor Latch Registers DLM and DLL 9.3.1FIFO Interrupt Mode Operation 9.316C550A UART FIFO Operation9.3.2FIFO Polled Mode Operation Parallel Host Interface 16C450/16C550A UART Intel Confidential536EX Chipset Developer’s Manual