Intel 536EX manual Figures, Intel Confidential, Contents

Contents
	9.2.1	Scratch Register (SCR)	95
	9.2.2	Modem Status Register (MSR)	95
	9.2.3	Line Status Register (LSR)	96
	9.2.4 Modem Control Register (MCR)		97
	9.2.5 Line Control Register (LCR)		97
	9.2.6 FIFO Control Register (FCR)		98
	9.2.7 Interrupt Identity Register (IIR)		99
	9.2.8 Interrupt Enable Register (IER)		100
	9.2.9	Transmitter Holding Register (THR)	100
	9.2.10	Receiver Buffer Register (RBR)	101
	9.2.11 Divisor Latch Registers (DLM and DLL)		101
	9.3 16C550A UART FIFO Operation		102
	9.3.1 FIFO Interrupt Mode Operation		102
	9.3.2 FIFO Polled Mode Operation		102
Figures
1	WDM Driver Block Diagram		8
2	VxD Mini Port Driver Block Diagram		9
3	Example of a Remote Connection		27
4	Modem-on-Hold: Incoming Voice Call in Data Mode		32
5	Modem-on-Hold: Initiating a Voice Call in Data Mode		33
6	Local Analog Loopback Test		37
7	Local Analog Loopback with Self-Test		37
8	T.30 HDLC Frame Format		66
9	CLASS 1 DTE-Generated HDLC Frame Information (AT+FTH=<mod>)		66
10	CLASS 1 DTE Reception of HDLC Frame Information (AT+FRH=<mod>)		66
11	UART Emulation in Intelsdb.VxD		92
12	FIFO Buffers for Transmitter and Receiver		93
13	Parallel Host Interface UART Register Bit Assignments		94
14	Scratch Register (SCR)		95
15	Modem Status Register (MSR)		95
16	Line Status Register (LSR)		96
17	Modem Control Register (MCR)		97
18	Line Control Register (LCR)		97
19	FIFO Control Register (FCR)		98
20	Interrupt Identity Register (IIR)		99
21	Interrupt Enable Register (IER)		100
22	Transmitter Holding Register (THR)		100
23	Receiver Buffer Register (RBR)		101
24	Divisor Latch Registers (DLM and DLL)		101

4 536EX Chipset Developer’s Manual

Intel Confidential