Parallel Host Interface 16C450/16C550A, Uart | Intel 536EX specification

Parallel Host Interface 16C450/16C550A UART

Parallel Host Interface 16C450/16C550A UART

Parallel Host Interface 16C450/16C550A

UART

9

9.1UART Emulation in the Controllerless Modem

When controllerless modems are used with Windows applications, the communication driver architecture eliminates the need for a UART emulation (see Section 1.1, “Controllerless Modem Driver Overview” on page 7). However, MS-DOS applications used with controllerless modems retain the need for a UART emulation. Therefore, Intel provides the Intelsdb.VXD driver, which includes this UART emulation and also interacts directly with the Windows VCOMM.VxD driver (see Figure 11).

Figure 11. UART Emulation in Intelsdb.VxD

MS-DOSAPPLICATION

Intelsdb.VXD

WINDOWS APPLICATION

UART EMULATION

HAM PORT DRIVER

VCOMM.VXD

The parallel host interface of the FastPath family emulate the electrical and register functions of a 16550A and 16C450 UART. Upon modem reset, the modem defaults to a 16C450. The host (DTE) can then configure the UART to function as a 16C550A UART.

In 16C450 emulation mode, the DTE and modem transfer data back and forth a byte at a time. In 16C550A emulation mode, the modem provides two 16-byte FIFO buffers, one for the transmitter and another for the receiver. Thus, up to 16 bytes of data may be sent to or received from the

92	536EX Chipset Developer’s Manual

Intel Confidential

Image 92

Intel 536EX Uart, Intel Confidential, Parallel Host Interface 16C450/16C550A UART, UART Emulation in Intelsdb.VxD

Contents

January 536EX ChipsetDeveloper’s Manual Intel Confidential 536EX Chipset Developer’s Manual Contents Contents Figures Tables Revision History DateRevision Description Introduction 1.1Controllerless Modem Driver Overview Figure 1. WDM Driver Block Diagram 1.1.2Windows 95 and WindowsUser applications Kernel - ring0 Figure 2. VxD Mini Port Driver Block Diagram 1.2V.90/V.92 and V.34 Data Modes 1.3Modem Connection Overview Table 3. DCE-to-ISPData Rates for V.90 Mode Table 1. DTE-to-DCEData Rates for Each ModeTable 2. DCE-to-DCEData Rates for Each Mode 1.4.1Sending Commands Table 4. DTE-ModemData Rate Response Codes 1.4.2AT Escape Sequences 1.4.3Dial Modifier Table 5. Data Mode Command Summary AT Command Summary TablesAT Command Summary Tables Table 5. Data Mode Command Summary Continued Result code type AT Command Summary Tables Generate data mode calling tone Table 6. V.44/V.42/V.42 bis MNP Command Summary AT Command Summary Tables Table 7. Fax Identity Command Summary Table 8. Fax Class 1 Command Summary Table 9. IS-101Voice Command Summary Table 10. Voice DTE→DCE Character Pairs Table 10. Voice DTE→DCE Character Pairs Continued Table 11. Voice DTE←DCE Character Pairs Table 13. S-RegisterSummary Table 11. Voice DTE←DCE Character Pairs ContinuedTable 12. Dial Modifiers Table 13. S-RegisterSummary Continued Data Mode AT COMMANDS Data Mode AT COMMANDS Table 14. Data Reporting Wn Mapping Figure 3. Example of a Remote ConnectionATW0 •ATW2 Examples +FMFR?, +FMDL?, +FREV? 3.8Modem-to-ModemConnection Data Rates 3.6Online Command Mode Escape Codes, On3.7Hanging Up Hn, S10, Zn, &D2 536EX Chipset Developer’s Manual +PMH=0 +PCW=0+VCID=1 +++AT 536EX Chipset Developer’s Manual hook to connect the call. Now you can answer the phone and talk. After completing your voice conversation, the modem will issue another +PMHF and ATO command to initiate a Quick Connect. If the server rejects the request to go on hold, the user can stay on line ATO command issued or disconnect from his initial data connection ATH command issued Table 16. Supported Modulation Types 3.9Diagnostic Testing S18, &Tn 3.9.1Local Analog Loopback AT&T1 3.9.2Local Analog Loopback With Self-TestAT&T8 LOCAL MODEMFigure 6. Local Analog Loopback Test Local Modem or Test Modem 3.10.1Time-IndependentEscape Sequence Licensing Requirements for Hayes Escape Sequence char1 = char2 = char3 = escape character S2 <char1><char2><char3><AT command><contents of S3>Format Table 18. Data Mode Command Descriptions 3.10.2Hayes* Escape Sequence 536EX Chipset Developer’s Manual Sn=x 536EX Chipset Developer’s Manual Data Mode AT COMMANDSIntel Confidential Data Mode AT COMMANDS AT&V0 536EX Chipset Developer’s Manual Definition Command DefaultIndication 1, 0, 536EX Chipset Developer’s Manual 1, 1, +ESR+ETBM +GMR +GSN+IFC +ILRR=m Data Mode AT COMMANDS <carrier> Description+MS=m see ‘m’ +PHSW= +PMHF<value> +PMHR 536EX Chipset Developer’s Manual Table 19. Operating Modes Error Correction and Data Compression4Error Correction and Data Compression Table 20. Resulting +ES Connection Types NOTES 536EX Chipset Developer’s Manual Error Correction and Data CompressionIntel Confidential 536EX Chipset Developer’s Manual +DR=m direction+DS=m <max string> 3768 +EFCS=m +ER=m +ES=m Fax Class 1 AT Commands 5.1Fax Identity Commands5.2Fax Class 1 Commands Fax Class 1 AT Commands Table 23. <mod> Selection Table Figure 8. T.30 HDLC Frame Format Table 24. Fax Mode Command Descriptions Table 24. Fax Mode Command Descriptions Continued +FRH=mRefer to Table 23 on page shown in Table 23 on page +FTH=m IS-101Voice Mode AT Commands IS-101Voice Mode AT Commands 6.2Relay Control Table 25. Voice Mode Command Descriptions6.1DTMF Detection Reporting +FLO=m m = <deassert>, <assert> m=<enable>, <report> +VDR=m m = <mask> +VEM=m Intel Confidential +VIP Preassigned Voice I/O Labels +VLS=m Voice I/O Primitive Codes Relay/Playback Control: cont +VSD=m +VRXm = <sds>, <sdi> Transmission: Range: m= <cml>, <vsr>, <scs>, <sel>+VSM=m Compression Method Selection: cont +VSP=m factory default is ‘0’ +VTS=m none Command DefaultDescription DTMF and Tone Generation: cont S-Registers S-RegistersTable 26. S-RegisterCommand Descriptions 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Table 27. Caller ID Tags for Formatted Reporting Caller IDCaller ID RING DATE = TIME = NMBR = NAME = DOE JOHN MESG = RING RING<DLE> R NMBR = Parallel Host Interface 16C450/16C550A UARTParallel Host Interface 16C450/16C550A UART Figure 11. UART Emulation in Intelsdb.VxD UART Transmitter Flow Diagram UART Receiver Flow Diagram REGISTER BIT NUMBERADDRESS NAME 9.2.1Scratch Register SCR 9.2.2Modem Status Register MSRFigure 14. Scratch Register SCR Figure 15. Modem Status Register MSR 9.2.3Line Status Register LSR Figure 16. Line Status Register LSR 9.2.4Modem Control Register MCR 9.2.5Line Control Register LCRFigure 17. Modem Control Register MCR Figure 18. Line Control Register LCR Figure 19. FIFO Control Register FCR 9.2.6FIFO Control Register FCRRegister Table 28. Interrupt Control Functions 9.2.7Interrupt Identity Register IIRFigure 20. Interrupt Identity Register IIR 9.2.8Interrupt Enable Register IER Figure 21. Interrupt Enable Register IER9.2.9Transmitter Holding Register THR Figure 22. Transmitter Holding Register THR 9.2.10Receiver Buffer Register RBR 9.2.11Divisor Latch Registers DLM and DLLFigure 23. Receiver Buffer Register RBR Figure 24. Divisor Latch Registers DLM and DLL 9.3.2FIFO Polled Mode Operation 9.316C550A UART FIFO Operation9.3.1FIFO Interrupt Mode Operation 536EX Chipset Developer’s Manual Intel ConfidentialParallel Host Interface 16C450/16C550A UART