Intel IXP12xx instruction

IXP12xx ATM OC12/Ethernet IP Router Example Design

Performance and Headroom Analysis

April, 2002

Document Number: 301144-001

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Intel manual IXP12xx ATM OC12/Ethernet IP Router Example Design

Contents

IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Measurement Environment OverviewAlternate Dram Timing Protocol Performance of IP over ATM vs. Ethernet KEY Workloads & Approaches to Testing the Example DesignSingle Cell PDU Workload Frame and PDU Length versus IP Packet Length Cycle and Instruction Budgets Multiple Cells/PDU WorkloadCycle Budgets to support Line Rates Cycles/cell Cells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7E Usec/frame = 1559 cycles/frame Simulated 29-byte packet performance1 Simulation Measurement Procedure and Results Simulated 40-byte and 1500-byte packet performance2 Hardware Measurement Procedure and ResultsHardware Measurement Results Hardware 29-byte packet performance Single-cell/PDU Performance using 133MHZ Dram 138 142 144 Hardware 40-byte packet performance9.5 88,300 518 Hardware 1500-byte packet performance517 ATM Queue to Core Throughput Queue to Core Measurement TechniqueEthernet Queue to Core Throughput Microengine Register and Microstore Headroom Resource Utilization and Headroom Analysis Sram Capacity Scratchpad RAM Capacity Sram and Sdram Bandwidth Sdram Capacity Buffer Allocation in Dram Appendix