Intel IXP12xx manual Overview, Measurement Environment, Alternate Dram Timing

Version 1.0, 4/10/02

IXP12xx ATM OC12/Ethernet IP Router Example Design

Performance and Headroom Analysis

OVERVIEW

This documents details the performance and headroom analysis done on the IXP12xx ATM OC12 / Ethernet IP Router Example Design. It covers the general performance aspects of the protocols; cycle and instruction budgets; testing under different workloads; and performance measurements in both, simulation and hardware environments.

This document also attempts to analyze the amount of headroom available in this design for customers to add additional features by providing microengine and memory utilization metrics.

Three different configurations are supported:

One ATM OC-12 port &	For use with the IXP1240/1250 with hardware CRC capability
eight 100Mbps Ethernet ports
Four ATM OC-3 ports &	Similar to the above configuration (requires the IXP1240/50), except
eight 100Mbps Ethernet ports	that it uses four OC-3 ports.
Two ATM OC-3 ports &	For use with the IXP1200 (which does not have hardware CRC
	capability). Instead, CRC computation is performed by two
four 100Mbps Ethernet ports
	microengines (thus the reduced data rates).

Since in each configuration aggregate Ethernet port bandwidth exceeds aggregate ATM port bandwidth, ATM port bandwidth is the limiting external factor. This example design supports full-duplex, full-bandwidth ATM communication on all available ATM ports.

The design is able to simultaneously transmit and receive any traffic pattern on all available ATM ports at line rate. Line rate means that no idle cells should appear on the ATM links. Furthermore, no ATM PHY FIFO overflows or Ethernet MAC FIFO overflows or underflows should occur.

MEASUREMENT ENVIRONMENT

Simulation and hardware performance testing was performed under the following conditions:

o232 MHz IXP1240 with an 80 MHz IX Bus

(IXP1200 measurements do not use the hardware-CRC on the IXP1240)

o133 MHz SDRAM – ‘-75’ speed-grade

(some results for 143 MHz (‘-7E’ speed-grade) are also provided where indicated)

Alternate DRAM Timing

The project ships with two FLASH files for two different DRAM speed grades.

atm_ether\tools\flash contains files for 133MHz (-75) and 143 MHz (-7E) DRAM. Most measurements were repeated with both settings to illustrate the sensitivity of the design to DRAM performance. Where not specifically mentioned in this document, the slower 133MHz settings were used.

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