Version 1.0, 4/10/02
Microstore utilization can be observed by opening a microengine list window with line numbers enabled, and recording the last line number plus 1. Available instructions = 2048 – used instructions.
Figure 12 shows the results for each of the three configurations.
The CRC Check and CRC Generate microengines apply only to the IXP1200 configuration. In the IXP1200 configuration the ATM Receive and IP Route functions run on the same microengine. See the Application Note for this example design for more detail on microengine and thread allocation.
Scratchpad RAM Capacity
There are 1024
This design uses 256 locations (25%) for statistics counters, including 16 counters for each of the 12 ports; plus global counters.
7 message queues consume 112 entries (11%), and a table to map port numbers to MAC addresses consumes 16 more entries. There are some smaller users of Scratchpad RAM locations that cause some address map fragmentation, but there are basically two blocks of about 256 entries available at 0x100 and 0x300.
SRAM Capacity
The IXM1240 Network Processor Base Card comes with 8MB of SRAM. This design is currently configured so it uses less than 4MB, leaving over 50% available.
As various configurations of this project may be integrated with other code that utilizes memory below 0x20000 (.5MB), the area below 0x20000 was simply left alone to avoid potential address map conflicts.
The SRAM portion of the IP Lookup Table begins at 0x20000, and can grow almost to 0x80000, (1.5MB).
For convenience, the same utilities are compiled to run on both Software and Hardware CRC configurations. Thus the current project taxes all configurations with a 64K location (256KB)
The VC Table occupies 0x50000 (320K) locations, corresponding to a 64K entry table with 5 locations per entry. The VC Miss Table has 8K additional entries consuming 0xA000 locations. All totaled, the VC tables consume 360K locations (1.4MB).
The system is configured with 16K Buffer Descriptors at 4 words each, consuming 64K locations (265KB).
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