Version 1.0, 4/10/02
Both the
Simulated 40-byte and 1500-byte packet performance2
The
HARDWARE MEASUREMENT PROCEDURE AND RESULTS
While simulation provides a high degree of visibility into the design, there are several important benefits to measuring on hardware:
1.The ability to do experiments on large numbers of packets. The simulator receives about 10 cells/second, whereas the hardware can receive
2.Unplanned error conditions occur regularly on the hardware due to hot plugging cables, optical and electrical noise,
3.The Transactor simulator does not model DRAM refresh overhead, and so configurations that are sensitive to DRAM bandwidth will notice a small performance hit on the hardware versus simulation.
To measure the design in the lab, an ADTECH AX/4000 is attached to the ATM ports, and a Smartbits 600 is attached to the 8 Ethernet ports.
Both pieces of equipment simultaneously generate traffic (at
After the experiment, the Octal MAC and the IXF6012 “Volga” PHY counters are checked for evidence of underflows or overflows. Specifically, for the PHY, idle cells sent or received are searched for, as these would indicate that the ATM links were not fully utilized.
The Counters_print() command at the VxWorks* command line also displays if the microcode discarded any packets, and why.
Hardware Measurement Results
Only the
ATM Transmit Rate is expressed as a percentage of
2Simulations for
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