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manual Dimension mm CN1A CN1B, 1c LPCI-7200S Layout Diagram Installation
Models:
LPCI-7200S
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Specs
Timing Characteristic
Install
1d LPCI-7200S with standard PCI bracket Layout Diagram
Warranty
Dimension
Hardware configuration
ERRNoError ERRInvalidBoardNumber ERRInvalidTimerMode ERRBoardNoInit
2.7 8254 for Timer Pacer Generation
LPCI-7200S PCI Bus Signaling
Page 19
Image 19
Dimension: mm
CN1A
CN1B
Figure 2.1(c)
LPCI-7200S
Layout Diagram
Installation
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Image 19
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Contents
NuDAQ→ / NuIPC→ PCI-7200 / cPCI-7200 / LPCI-7200S
12MB/S High Speed Digital Input/ Output Card User’s Guide
Recycled Paper
Page
Trademarks
Questions
Getting Service from ADLINK
ADLINK TECHNOLOGY INC
Detailed Company Information
Chapter 3 Register Format
Table of Contents
Chapter 2 Installation
Chapter 1 Introduction
Chapter 7 Limitations
Warranty
Chapter 5 C/C++ Libraries
Chapter 6 Double Buffer Mode Principle
Chapter 3 Register Structure & Format
How to Use This Guide
Installation
Introduction
Page
1.1 Applications
Introduction
Introduction
z Number of DO Channels 32 TTL compatible z Data Transfer Mode
1.2 Features
1.3 Specifications
‹ Digital I/O DIO z Number of DI Channels 32 TTL compatible
z Dimension
‹ General Specifications z Operating Temperature 0ºC to 60ºC
z Storage Temperature -20ºC to 80ºC
z Connector
1.4.1 Programming Library
1.4 Software Supporting
4 Introduction
1.4.5 DASYLabTM PRO
1.4.2 PCIS-LVIEW LabVIEW Driver
1.4.3 PCIS-VEE HP-VEE Driver
1.4.4 DAQBenchTM ActiveX Controls
6 Introduction
1.4.7 PCIS-ISG ISaGRAFTM driver
1.4.8 PCIS-ICL InControlTM Driver
1.4.9 PCIS-OPC OPC Server
2.1 What Included
Installation
Installation
8 Installation
2.3 Device Installation for Windows Systems
2.2 Unpacking
You are now ready to install your PCI-7200
PCI -Bus Controller
2.4 PCI-7200/cPCI-7200/LPCI-7200S’s Layout
Figure 2.1a PCI-7200 Layout Diagram Installation
ALTERA
Figure 2.1b cPCI-7200 Layout Diagram 10 Installation
Figure 2.1c LPCI-7200S Layout Diagram Installation
Dimension mm CN1A CN1B
Figure 2.1d LPCI-7200S with standard PCI bracket Layout Diagram
Dimension mm
12 Installation
Installation
2.5 Hardware Installation Outline
Hardware configuration
Installation Procedures
2.6.1 PCI-7200 Pin Assignments
2.6 Connector Pin Assignments
Figure 2.2 CN1 Pin Assignments 14 Installation
DI12
Figure 2.3 CN2 Pin Assignments Installation
DI10
DI11
9921
2.6.2 cPCI-7200 Pin Assignments
16 Installation
9820
Installation
2.6.3 LPCI-7200S Pin Assignments
Figure 2.5 CN1A Pin Assignments
Figure 2.6 CN1B Pin Assignments
18 Installation
Timer
2.7 8254 for Timer Pacer Generation
Timer
4MHz Clock
2.9 Onboard Pull-ups and Terminations in digital input
2.8 LPCI-7200S PCI Bus Signaling
20 Installation
3.1 I/O Registers Format
Register Format
Register Format
Address BASE + Attribute READ Only Data Format
3.2 Digital Input Register BASE +
3.3 Digital Output Register BASE +
3.4 DIO Status & Control Register BASE +
Register Format
‹ Digital Input Mode Setting
IACK Input ACK Enable
‹ Digital Output Mode Setting
‹ Interrupt Control
3.5 Interrupt Status & Control Register BASE + 1C
‹ Digital I/O FIFO Status
Address BASE + 1C Attribute READ/WRITE Data Format
‹ Timer Configuration Control
T0EN Interrupt is triggered by timer 0 output
Register Format
‹ FIFO Control and Status cPCI-7200 only
‹ IREQ Polarity Selection
26 Register Format
Register Format
3.6 8254 Timer Registers BASE +
Page
4.1 Direct Program Control
Operation Theory
Operation Theory
Timer
4.2 Timer Pacer Mode
CLK0 Timer
Timer
Operation Theory
4.3 External Clock Mode
4.4 Handshaking
IREQ & IACK for Digital Input
32 Operation Theory
OREQ & OACK for Digital Output
t h ≥ 60ns
4.5 Timing Characteristic
IN IREQ
D10~DI31
valid data
IN IREQ
IN IACK
D10~DI31
Operation Theory
OUTREQO REQt2 OUTACK
DO0~Do31valid datavalid data
t1 19ns t2 1 PCI CLK Cycle t3 5 PCI CLK Cycle
Page
C/C++ Libraries
5.1 Libraries Installation
C/C++ Libraries
38 C/C++ Libraries
5.2 Programming Guide
5.2.1 Naming Convention
5.2.2 Data Types
Visual C++ Windows
5.3 7200Initial
@ Description
@ Syntax
@ Syntax
5.4 7200SwitchCardNo
5.5 7200AUXDI
@ Description
@ Syntax
5.6 7200AUXDIChannel
5.7 7200AUXDO
@ Description
@ Syntax
5.8 7200AUXDOChannel
5.9 7200DI
@ Description
@ Syntax
5.10 7200DIChannel
5.11 7200DO
@ Description
Visual C++ Windows
5.12 7200DOChannel
@ Description
@ Syntax
Visual C++ Windows
5.13 7200AllocDMAMem
@ Description
@ Syntax
@ Syntax
5.14 7200FreeDMAMem
5.15 7200AllocDBDMAMem
@ Description
@ Description
5.16 7200FreeDBDMAMem
5.17 7200DIDMAStart
@ Return Code
48 C/C++ Libraries
C/C++ DOS
@ Syntax
Visual C++ Windows
Visual Basic Windows
@ Description
5.18 7200DIDMAStatus
clearfifo
@ Return Code
@ Syntax
5.19 7200DIDMAStop
5.20 7200DblBufferMode
@ Description
@ Syntax
5.21 7200CheckHalfReady
5.22 7200DblBufferTransfer
@ Description
@ Syntax
5.23 7200GetOverrunStatus
5.24 7200DODMAStart
@ Description
@ Return Code
5.25 7200DODMAStatus
C/C++ DOS
@ Argument
@ Return Code
5.26 7200DODMAStop
C/C++ DOS
@ Argument
Visual C++ Windows
5.27 7200DITimer
@ Description
@ Syntax
@ Description
5.28 7200DOTimer
ERRNoError ERRInvalidBoardNumber ERRInvalidTimerMode ERRBoardNoInit
@ Return Code
C/C++ DOS
@ Syntax
Visual C++ Windows
Visual Basic Windows
Double Buffer Mode Principle
Double Buffer Mode Principle
60 Double Buffer Mode Principle
Limitations
Limitations
Page
Product Warranty/Service
Warranty Policy
