Intel LPCI-7200S manual 48 C/C++ Libraries

Bus Mastering DMA mode of the PCI-7200:

PCI bus mastering offers the highest possible speed available on the PCI-7200. When the function _7200_DI_DMA_Start is executed, it will enable PCI bus master operation. This is conceptually similar to DMA (Direct Memory Access) transfers in a PC but it is really PCI bus mastering. It does not use an 8237-style DMA controller in the host computer and therefore isn't blocked in

64k max groups. PCI-7200 bus mastering works as follows:

1.To set up bus mastering, first do all normal PCI-7200 initialization necessary to control the board in status mode. This includes testing for the presence of the PCI BIOS, determining the base addresses, slot number, vendor and device ID's, I/O, or memory, space allocation, etc. Please make sure the PCI-7200 is plugged in a bus master slot, otherwise this function will not be workable.

2.Load the PCI controller with the count and 32-bit physical address of the start of previously allocated destination memory, which will accept data. This count is the number of bytes (not long words) transferred during the bus master operation and can be a large number up to 64 million (2^26) bytes. Since PCI-7200 transfers are always long words, this equals 16 million long words (2^24).

3.After the input sampling is started, the input data is stored in the FIFO of PCI controller. Each bus mastering data transfer continually tests if any data in the FIFO and then blocks transfer, the system will continuously loop until the conditions are satisfied again but will not exit the block transfer cycle if the block count is not complete. If there is momentarily no input data, the PCI-7200 will relinquish the bus temporarily but returns immediately when more input data appears. This operation continues until the whole block is done.

4.This operation proceeds transparently until the PCI controller transfer byte count is reached. All normal PCI bus operations applied here, such as a receiver that cannot accept the transfers, higher priority devices requesting the PCI bus, etc. Remember that only one PCI initiator can have bus mastering at any one time. However, review the PCI priority and "fairness" rules. Also study the effects of the Latency Timer. Additionaly, be aware that the PCI priority strategy (round robin rotated, fixed priority, custom, etc.) is unique to each host PC and is explicitly not defined by the PCI standard. You must determine this priority scheme for your own PC (or replace it).

The interrupt request from the PCI controller can be optionally set up to indicate that this loanword count is complete although this can also be determined by polling the PCI controller.

48 • C/C++ Libraries