Intel LPCI-7200S manual 3.6 8254 Timer Registers BASE +, Register Format

Models: LPCI-7200S

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3.6 8254 Timer Registers (BASE + 0)

3.6 8254 Timer Registers (BASE + 0)

The 8254 timer/counter IC occupies 4 I/O address. Users can refer to Tundra's or Intel's data sheet for a full description of the 8254 features. Download the

8254 data sheet from the following web site:

http://support.intel.com/support/controllers/peripheral/231164.htm or

http://www.tundra.com (for Tundra’s 82C54 datasheet).

Address

Read

Write

 

 

 

Base + 0

Counter 0

Counter 0

Base + 4

Counter 1

Counter 1

Base + 8

Counter 2

Counter 2

Base + C

---

CLK Control CW0

Register Format 27

Page 35
Image 35
Intel LPCI-7200S manual 3.6 8254 Timer Registers BASE +, Register Format