4.2 Timer Pacer Mode
The digital I/O access control is clocked by timer pacer, which is generated by an interval programming timer/counter chip (8254). There are three timers on the 8254. Timer 0 is used to generate timer pacer for digital input and timer 1 is used for digital output. The configuration is illustrated as below.
“H”
“H”
4MHz Clock
“H”
8254 Timer/Counter
CLK0 | Timer 0 | |
GATE0 | OUT0 | |
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| |
CLK1 | Timer 1 | |
GATE1 | OUT1 | |
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| |
CLK2 | Timer 2 | |
OUT2 | ||
GATE2 |
Digital Input Timer Pacer
Digital Output Timer Pacer
The operation sequences are:
1.Define the frequency (timer pacer rate)
2.The digital input data are saved in FIFO after a timer pacer pulse is generated. The sampling is controlled by timer pacer.
3.The data saved in FIFO will be transferred to main memory of the computer system directly and automatically. This is controlled by bus mastering DMA control, this function is supported by PCI controller chip.
The operation flow is show as following:
8254 Timer/Counter
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| 1 |
| CLK0 Timer 0 |
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| |
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| To Digital Input Trigger | |
| GATE0 | OUT0 |
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Latch Digital Input
PC's Main Memory
3
2
Bus mastering | Digital Input FIFO |
DMA data Transfer |
