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Intel SE7501WV2 Revision 1.0 Intel reference number C25653-001 , Table 34. Primary Master and Slave Adapters Sub-menu Selections , Table 35. Processor Settings Sub-menu

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BIOS Intel® Server Board SE7501WV2 TPS

Revision 1.0

Intel reference number C25653-001

100

Table 34. Primary Master and Slave Adapters Sub-menu Selections

Feature Option Description

Type None

Auto

Auto allows the system to attempt auto-detection of the drive type.

None informs the system to ignore this drive.

LBA Mode Control Disabled

Enabled

Disabled by default if no devices are detected, otherwise the setting is auto

detected

This field is informational only.

Multi-Sector

Transfer

Disabled

2 Sectors

4 Sectors

8 Sectors

16 Sectors

Displays the number of sectors per block for multiple sector transfers.

This field is informational only.

This option is viewable only if an IDE HDD is detected.

PIO Mode Standard

1

2

3

3 / DMA 1

4

4 / DMA 2

Displays the method for moving data to/from the drive.

This field is informational only.

Ultra DMA 2

4

Displays the method for moving data to/from the drive.

This field is informational only.

Table 35. Processor Settings Sub-menu

Feature Option Description

Processor Type Information Only Displays the type of processor(s) installed

Processor POST Speed Information Only Displays the measured processor speed

Processor Retest Disabled

Enabled

If enabled, BIOS will clear historical processor status and retest

all processors on the next boot.

Hyper-Threading Technology Disabled

Enabled

Controls the state of Hyper-Threading Technology in the

processors.

Processor 1 CPUID CPU ID

Non Installed

Disabled

Reports CPUID for Processor 1, if present. If empty, reports Not

Installed. If disabled by the BMC, reports Disabled.

Processor 1 L2 Cache Size N/A Reports L2 Cache Size for Processor 1.

Processor 2 CPUID CPU ID

Non Installed

Disabled

Reports CPUID of Processor 2 , if present. If empty, reports Not

Installed. If disabled by the BMC, reports Disabled.

Processor 2 L2 Cache Size N/A Reports L2 Cache Size for Processor 2.

6.20.2.5 Advanced Menu Selections The following tables describe the menu options and associated sub-menus available on the Advanced Menu.

Contents

Main Intel Server Board SE7501WV2 Technical Product Specification Revision History Disclaimers Table of Contents Page Page Page Page Page Page Page Page List of Figures List of Tables Page Page Page 1. Introduction 2. SE7501WV2 Server Board Overview 2.1 SE7501WV2 Feature Set Page Page 3. Functional Architecture 3.1 Processor and Memory Subsystem 3.1.1 Processor Support Page 3.1.2 Memory Subsystem Page Page Page 3.2 Intel E7501 Chipset 3.2.1 MCH Memory Architecture 3.2.2 MCH North Bridge 3.2.3 P64H2 3.2.4 ICH3-S Page 3.3 Super I/O 3.3.1 GPIOs 3.3.2 Serial Ports Page Page Page 3.3.3 BIOS Flash 4. Configuration and Initialization 4.1.1 Main Memory 4.1.2 Memory Shadowing 4.1.3 System Management Mode Handling 4.2 I/O Map 4.3 Accessing Configuration Space 4.3.1 CONFIG_ADDRESS Register 00 Register Device Bus Number Reserved Enable bit (1 = enabled, 0 = disabled) 4.4 Hardware Initialization 4.5 Clock Generation and Distribution Page Page 4.6 PCI I/O Subsystem 4.6.1 PCI Subsystem 4.6.2 P32-A: 32-bit, 33-MHz PCI Subsystem 4.6.3 P64-B and P64-C: 64-bit, 100-MHz PCI-X Subsystem Page 4.7 Ultra320 SCSI 4.8 ATA-100 4.9 Video Controller 4.9.1 Video Modes Revision 1.0 Intel reference number C25653-001 Table 17. Video Modes 4.9.2 Video Memory Interface Table 18. Video Memory Interface 4.9.3 Front Panel Video Memory 4.10 Network Interface Controller (NIC) 4.10.1 NIC Connector and Status LEDs 4.11 Interrupt Routing 4.11.1 Legacy Interrupt Routing 4.11.2 Serialized IRQ Support 4.11.3 APIC Interrupt Routing Revision 1.0 Intel reference number C25653-001 Table 20. Intel Server Board SE7501WV2 Interrupt Mapping Page Server Management Intel Server Board SE7501WV2 TPS Revision 1.0 Intel reference number C25653-001 Figure 9. Intel Server Board SE7501WV2 Sahalee BMC Block Diagram 5. Server Management BASEBOARD - Chassis ID - Baseboard ID - Power State INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB) To Power Distributio 5.1 Sahalee Baseboard Management Controller (BMC) Revision 1.0 Intel reference number C25653-001 Page Page Page Revision 1.0 Intel reference number C25653-001 Table 22. ADM1026 Input Definition 5.1.1 Fault Resilient Booting 5.2 System Reset Control 5.2.1 Power-up Reset 5.2.2 Hard Reset 5.2.3 Soft Reset 5.3 Intelligent Platform Management Buses (IPMB) 5.4 Inter Chassis Management Bus (ICMB) 5.5 Error Reporting 5.5.1 Error Sources and Types 5.5.2 PCI Bus Errors 5.5.3 Intel Xeon Processor Bus Errors 5.5.4 Memory Bus Errors Page Page Revision 1.0 Intel reference number C25653-001 Table 25. Boot Block POST Progress Codes Page Page 5.5.6 Temperature Sensors 6. BIOS 6.1 System Flash ROM Layout 6.2 BIOS Boot Specification Compliance 6.3 Memory 6.3.1 Memory Configuration 6.3.2 Memory Sizing and Initialization 6.3.3 ECC Initialization 6.3.4 Memory Remapping 6.3.5 DIMM Failure LED 6.4 Processors 6.5 Extended System Configuration Data (ESCD), Plug and Play (PnP) 6.5.1 Resource Allocation 6.5.2 PnP ISA Auto-Configuration 6.5.3 PCI Auto-Configuration 6.6 NVRAM API 6.7 Legacy ISA Configuration 6.8 Automatic Detection of Video Adapters 6.9 Keyboard / Mouse Configuration 6.9.1 Boot without Keyboard and/or Mouse 6.10 Floppy Drives 6.11 Universal Serial Bus (USB) 6.12 BIOS Supported Server Management Features 6.12.1 IPMI 6.12.2 Advanced Configuration and Power Interface (ACPI) 6.12.3 Wake Events 6.12.4 Front Panel Switches 6.12.5 Wired For Management (WFM) 6.12.6 PXE BIOS Support 6.12.7 BIOS Recommendations 6.13 Console Redirection 6.13.1 Operation 6.13.2 Keystroke Mappings Page Page 6.13.3 Limitations 6.14 Emergency Management Port (EMP) 6.14.1 Serial Ports 6.14.2 Interaction with BIOS Console Redirection 6.15 Service Partition Boot 6.16 System Management BIOS (SMBIOS) Revision 1.0 Intel reference number C25653-001 Table 30. SMBIOS Header Structure 6.17 Microsoft* Windows* Compatibility 6.17.1 Quiet Boot 6.18 BIOS Serviceabilty Features 6.18.1 CMOS Reset 6.19 BIOS Updates 6.19.1 Flash Update Utility 6.19.2 Loading the System BIOS 6.19.3 User Binary Area 6.19.4 BIOS Recovery Mode 6.19.5 Rolling BIOS and On-line updates 6.20 BIOS and System Setup 6.20.1 BIOS Setup Utility Page Page Page Revision 1.0 Intel reference number C25653-001 Table 33. Main Menu Selections Revision 1.0 Intel reference number C25653-001 Table 34. Primary Master and Slave Adapters Sub-menu Selections Table 35. Processor Settings Sub-menu Revision 1.0 Intel reference number C25653-001 Table 36. Advanced Menu Selections Table 37. Advanced Chipset Control Sub-menu Selections Table 38. PCI Configuration Sub-menu Selections Revision 1.0 Intel reference number C25653-001 Table 39. PCI Device, Embedded Devices Table 40. I/O Device/Peripheral Configuration Sub-menu Selections Revision 1.0 Intel reference number C25653-001 Table 41. Memory Configuration Menu Selections 6.20.2.6 Security Menu Selections Table 42. Security Menu Selections Revision 1.0 Intel reference number C25653-001 6.20.2.7 Server Menu Selections Table 43. Server Menu Selections Revision 1.0 Intel reference number C25653-001 Table 44. System Management Sub-menu Selections Revision 1.0 Intel reference number C25653-001 Table 45. Serial Console Redirection Sub-menu Selections Table 46. Event Log Configuration Sub-menu Selections Revision 1.0 Intel reference number C25653-001 Table 47. Fault Resilient Boot Sub-menu Selections Table 48. Boot Menu Selections Table 49. Boot Device Priority Selections Revision 1.0 Intel reference number C25653-001 Revision 1.0 Intel reference number C25653-001 6.21 BIOS Security Features 6.21.1 Operating Model Table 53. Security Features Operating Model 6.22 Password Protection 6.23 Inactivity Timer 6.24 Hot Key Activation 6.25 Password Clear Jumper 6.26 Secure Mode (Unattended start) 6.27 Front Panel Lock 6.29 PS/2 Keyboard and Mouse Lock 6.30 Secure Boot (Unattended Start) 6.31 Error Handling 6.31.1 Error Sources and Types 6.32 SMI Handler 6.33 PCI Bus Error 6.34 Processor Bus Error 6.35 Single-Bit ECC Error Throttling Prevention 6.36 System Limit Error 6.37 Boot Event 6.38 Fault Resilient Booting (FRB) 6.38.1 FRB3 6.38.2 FRB2 Page 6.39 Boot Monitoring 6.39.1 Purpose Revision 1.0 Intel reference number C25653-001 Figure 10. BIOS Boot Monitoring Flowchart 6.40 Logging Format Conventions 6.40.1 Memory Error Events Revision 1.0 Intel reference number C25653-001 Table 54. Memory Error Event Data Field Contents Revision 1.0 Intel reference number C25653-001 6.40.2 PCI Error Events The following table defines the data byte formats for PCI bus-related errors logged by the BIOS. Table 55. PCI Error Event Data Field Contents Revision 1.0 Intel reference number C25653-001 6.40.3 FRB-2 Error Events The following table defines the data byte formats for FRB-2 errors logged by the BIOS. Table 57. FRB-2 Event Data Field Contents 6.41 POST Codes, Error Messages, and Error Codes 6.41.1 POST Progress Code LEDs 6.41.2 POST Error Codes and Messages Revision 1.0 Intel reference number C25653-001 Table 61. Extended POST Error Messages and Codes Revision 1.0 Intel reference number C25653-001 6.41.3 POST Error Beep Codes 6.41.4 BIOS Recovery Beep Codes Table 62. BIOS Recovery Beep Codes Revision 1.0 Intel reference number C25653-001 6.41.5 Bootblock Error Beep Codes Table 63. Bootblock Error Beep Codes Table 64. Three-beep Boot Block Memory Failure Error Codes 6.42 "POST Error Pause" Option 6.43 SE7501WV2 Server Board BIOS Runtime APIs 6.44 INT 15 Extensions 6.44.1 Cache Services 6.44.2 Intel ID String 6.44.3 Processor Information Processor Information returns information about the system processors. 6.44.4 Extended NVRAM Services 6.44.5 IPMB Services 6.45 Multiple Processor Support (MPS) 6.45.1 Multiprocessor Specification Support 6.45.2 Multiple Processor Support 6.46 Hyper-Threading Technology 6.47 OEM Customization 6.48 User Binary Page 6.48.1 Scan Point Definitions 6.48.2 Format of the User Binary Information Structure 6.48.3 OEM Splash Screen 6.48.4 Localization 7. SE7501WV2 ACPI Implementation 7.1 ACPI 7.1.1 Front Panel Switches Page 7.1.2 Wake up Sources (ACPI and Legacy) Revision 1.0 Intel reference number C25653-001 8. SE7501WV2 Connectors 8.1 Power Connectors Table 69. Power Connector Pin-out (J3J1) Table 70. Power Supply Signal Connector (J1J1) 8.2 Memory Module Connector Table 72. DIMM Connectors (J5F1, J5F2, J5F3, J6F1, J6F2, J6F3) Revision 1.0 Intel reference number C25653-001 8.3 Processor Socket Table 73. Socket 604 Processor Socket Pinout Page 8.4 System Management Headers 8.4.1 ICMB Header 8.4.2 OEM IPMB Header 8.5 PCI I/O Riser Slot Connector Revision 1.0 Intel reference number C25653-001 Table 77. P64-C Low-Profile Riser Slot Pin-out Page Revision 1.0 Intel reference number C25653-001 8.6 Front Panel Connectors Table 78. 34-pin Front Panel Connector Signal Descriptions Revision 1.0 Intel reference number C25653-001 148 8.6.1 High Density 100-Pin Floppy / Front Panel / IDE Connector (J2G1) Table 80. High density 100-Pin Floppy/Front Panel/IDE Connector Pin out (J2G1) Page Revision 1.0 Intel reference number C25653-001 150 8.6.2 VGA Connector The following table details the pin-out of the VGA connector (located on the rear I/O panel). Table 81. VGA Connector Pin-out (J8A1) 8.6.3 SCSI Connectors 8.6.4 NIC Connector Table 83. Stacked Dual RJ-45 Connector Pin-out (JA6A1) 8.6.5 ATA RAID Connectors Revision 1.0 Intel reference number C25653-001 153 Table 85. ATA-100 Legacy 40-pin Connector Pinout (J1G2) 8.6.6 USB Connector The following table provides the pin-out for both external USB connectors. Table 86. USB Connectors Pin-out (J4A1, J9A1) Revision 1.0 Intel reference number C25653-001 154 8.6.7 Floppy Connector Table 88. Legacy 34-pin Floppy Connector Pin-out (J1G1) 8.6.8 Serial Port Connector 8.6.9 Keyboard and Mouse Connector 8.7 Miscellaneous Headers 8.7.1 Fan Headers 9. Configuration Jumpers 9.1 System Recovery and Update Jumpers Page 10. General Specifications 10.1 Absolute Maximum Ratings 10.2 Power Information 10.2.1 SE7501WV2 Server Board Power Budget 10.3 Power Supply Specifications 10.3.1 Power Timing Revision 1.0 Intel reference number C25653-001 161 Figure 12. Output Voltage Timing Table 99. Voltage Timing Parameters Table 100. Turn On / Off Timing Revision 1.0 Intel reference number C25653-001 162 Figure 13. Turn On / Off Timing 10.3.2 Voltage Recovery Timing Specifications 11. Regulatory and Integration Information 11.1 Product Regulatory Compliance 11.1.1 Product Safety Compliance 11.1.2 Product EMC Compliance 11.1.3 Product Regulatory Compliance Markings 11.2 Electromagnetic Compatibility Notices 11.3 Replacing the Back up Battery Page Intel Server Board SE7501WV2 TPS Mechanical Specifications Revision 1.0 Intel reference number C25653-001 167 12. Mechanical Specifications The following figure shows the SE7501WV2 server board mechanical drawing. 12.1 PCI Riser Cards 12.1.1 1-Slot 3.3V PCI Riser Card 12.1.2 3-Slot 3.3V PCI Riser Card Appendix A: Glossary