Intel® Server Board SE7501WV2 TPSBIOS

Table 54. Memory Error Event Data Field Contents

Field

IPMI Definition

 

BIOS-Specific Implementation

Generator ID

7:1 System software ID or IPMB

If BIOS is the source:

 

slave address.

7:4 0x3 for system BIOS

 

1=ID is system software ID

 

3:1

 

0=ID is IPMB slave address.

 

1 = Format revision, Revision of the data format for OEM

 

 

 

data bytes 2 and 3, For this revision of the specification,

 

 

 

set this field to 1. All other revisions are reserved for now.

 

 

 

0

 

 

 

1 = ID is system software ID.

 

 

As a result, the generator ID byte will start from 0x31 and go

 

 

up to 0x3f, in increments of 2 for events logged by the BIOS.

 

 

If BMC is the source:

 

 

7:1 7 bit I2C Slave Address

 

 

0

0 = ID is IPMB Slave Address

 

 

 

Sensor Type

Sensor Type Codes, in the Intelligent

0xC for memory errors

 

Management Platform Interface

 

 

 

Specification v1.5.

 

 

 

 

 

Sensor Number

Number of sensor that generated this

Unique value for each type of event because IPMI

 

event

specification requires it that way. This field has no other

 

 

significance. Should not be displayed to the end user if the

 

 

event is logged by BIOS. For Single Bit memory errors the

 

 

value is 0x08, for Multi-bit memory errors, the value is 0x08.

 

 

For Single Bit memory error loggin disabled, the value is 0x09.

Type code

0x6F if event offsets are specific to

0x6F

 

the sensor

 

 

 

 

 

Event Data 1

7:6

Follow IPMI definition. If either of the two data bytes following

 

00 = unspecified byte 2

this do not have any data, that byte should be set to 0xff, and

 

10 = OEM code in byte 2.

the appropriate filed in event data 1 should indicate that that it

 

is unspecified.

 

5:4

 

According to Table 30.3 in the Intelligent Management

 

00 = unspecified byte 3

 

Platform Interface Specification, 3:0 is 0 for single bit error and

 

10 = OEM code in byte 3. (BIOS

1 for multi-bit error.

 

will not use encodings 01 and

 

 

 

11 for errors covered by this

 

 

 

document.).

 

 

 

3:0

 

 

 

Offset from Event Trigger for

 

 

 

discrete event state.

 

 

Event Data 2

7:0 OEM code 2 or unspecified.

If format rev is 1 and if this byte is specified, Syndrome Byte.

 

 

 

Event Data 3

7:0 OEM code 3 or unspecified.

For format rev 1, if this byte is specified,

 

 

7:6 Zero based Memory card number. Matches the number of

 

 

type 16 entry in SMBIOS table. For example, card 0

 

 

corresponds to the first type 16 entry in SMBIOS tables. If all

 

 

DIMMs are onboard, this field will always be 0.

 

 

5:0 Zero based DIMM number on the card. DIMM 0

 

 

corresponds to the first type 17 record in SMBIOS tables for

 

 

that memory card.

Revision 1.0

119

 

Intel reference number C25653-001

Page 119
Image 119
Intel SE7501WV2 manual Memory Error Event Data Field Contents

SE7501WV2 specifications

The Intel SE7501WV2 is a versatile server motherboard designed to meet the demanding needs of modern computing environments. Engineered with a focus on performance, reliability, and flexibility, this motherboard is tailored for a range of applications, from entry-level servers to high-performance computing tasks.

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