LG Electronics LG-C320 service manual Memory support and LCD interface, EBI2

3. TECHNICAL BRIEF

3.1.2 Memory support (and LCD interface)

The QSC62x0 device has two external bus interface (EBI) ports: EBI1 and EBI2.

EBI1 supports high-speed synchronous dynamic devices. Its memory controller supports the new mobile DDR SDRAM memories with its higher bandwidth and ability to run at high clock frequencies. This interface supports the high-bandwidth, high-density, and low-latency requirements of the QSC’s advanced on-chip capabilities such as the ARM9 processor, highperformance graphics, and video applications.

EBI2 is the slower speed interface intended to support memory devices such as NAND flash and asynchronous SRAM, peripheral devices such as LCDs, and the UBM receiver for multicast or broadcast reception (QSC6270 only). In addition, EBI2 is required to support a synchronous-burst AAD NOR flash to enable a NOR/DDR SDRAM memory configuration because the simultaneous mode (NOR, SDRAM) is not supported on the EBI1 bus.

The ARM926EJ-S microprocessor is a cached processor and all its accesses to external memory use burst techniques of four or eight 32-bit words when the memory region is declared to be cacheable/bufferable. To take advantage of this QSC higher performance feature, data from memories must satisfy the requirements for these burst accesses.

		EBI1
	CLK	DDR_M_CLK_N
	CKE	DDR_CKE[0]
	_CS	DDR_CS[0]_N
	_RAS	DDR_RAS_N
SDRAM	_CAS	DDR_CAS_N
512Mbit)	_WED	DDR__WE__N
	DQM	DDR_DQM[0:1]
	ADDR	DDR_A[0:13]	QSC6270
	DQ	DDR_D[0:15]	(3G disable)
External		MSD_D[0:3]
Memory
( MICRO SD)		MSD_CMD
		MSD_CLK

	EBI2
	NANDCS__N
			_CE
	NANDLB	_N	ALE
	NANDUB	_N	CLE
	NAND_OE_N		_RE	NAND Flash
	NAND_WEN		_WE	(1Gbit)
	NANDBSY_N		RY_BY
NAND_WNP			_WP
NAND_DATA[ 0: 15]
			IO[ 1: 16]

SIM_CLK
SIM_RST_N	USIM
SIM_DATA	(SIM PLUS)
MUSIM_DM
MUSIM_DP

Figure 3.1.2.1 The memory control blocks of C320

LGE Internal Use Only	- 18 -	Copyright © 2010 LG Electronics. Inc. All right reserved.
		Only for training and service purposes