LG Electronics LG-C320 External memory interface, EBI1 Features, Sdram, EBI2 Features

3. TECHNICAL BRIEF

3.3.2 External memory interface

The QSC62x0 device has two external bus interface (EBI) ports: EBI1 and EBI2.

EBI1 supports high-speed synchronous dynamic devices. Its memory controller supports the new mobile DDR SDRAM memories with its higher bandwidth and ability to run at high clock frequencies. This interface supports the high-bandwidth, high-density, and low-latency requirements of the QSC’s advanced on-chip capabilities such as the ARM9 processor, highperformance graphics, and video applications.

EBI2 is the slower speed interface intended to support memory devices such as NAND flash and asynchronous SRAM, peripheral devices such as LCDs, and the UBM receiver for multicast or broadcast reception (QSC6270 only). In addition, EBI2 is required to support a synchronous-burst AAD NOR flash to enable a NOR/DDR SDRAM memory configuration because the simultaneous mode (NOR, SDRAM) is not supported on the EBI1 bus.

EBI1 Features

EBI1 is a high-performance external memory interface for the QSC62x0 digital block that supports DDR SDRAM devices Specifically, the following memory devices are supported on EBI1:

̰SDRAM

-16-bit low-power DDR SDRAM

-Minimum size per chip-select: 16 MB (128 Mbit)

-Maximum size per chip-select: 128 MB (1 Gbit, 1 k columns only) Characteristics of the EBI1 clock are listed below:

-Maximum clock rate is 92 MHz, defined by the AMSS software.

-The EBI1 memory controller clock is synchronous to the bus clock (HCLK).

EBI2 Features

EBI2 is used to interface with slower memory and peripheral devices (NAND flash, burst NOR, LCDs, etc.). The following EBI2 devices are supported:

̰NAND flash

-8/16 bit, single-level cell (SLC)/multi-level cell (MLC) 512/2048-byte page devices -DMA support

-Boot-up capability from the above devices

̰Burst NOR flash

-16-bit multiplexed AAD burst NOR devices

̰8/16/18-bit (write only) LCD devices (both Motorola and Intel style) Characteristics of the EBI2 clock are listed below:

̰The maximum clock rate is 46 MHz, defined by the AMSS software.

̰The EBI2 memory controller operates at HCLK/2.

̰Broadcasting and multicasting (QSC6270 only, with MBP1600 IC) are based on: -Wideband MediaFLO™, DBV-H, and ISDB-T

Asynchronous/burst controller (EBI1 and EBI2)

The external memory controller (xmem_ctlr) forms the asynchronous/burst controller for both EBI1 and EBI2 in the QSC62x0 device. The controller is generic in terms of its software programmable options and can be customized when used for EBI1 and EBI2. This block has been enhanced in the QSC62x0 device to support 32-bit burst memories and byte masking during write operations.

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