DS5001FP
5 of 26
33, 35,
37
9 and A15 respectively.
71, 69,
67, 65,
61, 59,
57, 55
28, 26,
24, 23,
21, 20,
19, 18
BD7–0
Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
CE1 and CE2. Read/write access is controlled by R/ W. BD7–0 connect directly to an
SRAM, and optionally to a real-time clock or other peripheral.
10 37 R/ W
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
74 29 CE1
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium-backed. It
remains in a logic high inactive state when VCC falls below VLI.
72 N/A CE1N Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
233
CE2
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE2
into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when
VCC falls below VLI.
63 22 CE3
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE3
into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when
VCC falls below VLI.
62 N/A CE4
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
CE4 is lithium-backed and remains at a logic high when VCC < VLI.
78 N/A PE1
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283. PE1 is lithium-bac ked and remains at a logic high when VCC falls
below VLI. Connect PE1 to battery-backed functions only.
3N/APE2
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1. PE2 is lithium-backed and remains at a logic high when VCC
falls below VLI. Connect PE2 to battery-backed functions only.
22 N/A PE3
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
23 N/A PE4
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
32 N/A PROG
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
42 N/A VRST
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC)
has fallen below the VCCmin level and the micro is in a reset state. When this occurs, the
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
43 N/A PF
This output goes to a logic 0 to indicate that VCC < VLI and the micro has switched to
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
VCC = 0V. The normal application of this signal is to control lithium powered current to
isolate battery-backed functions from non-battery-backed functions.
14 40 MSEL
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
73 NC No Connect.