Maxim DS5001FP specifications BYTE-WIDE ADDRESS/DATA BUS Timing

DS5001FP

AC CHARACTERISTICS (continued)

BYTE-WIDE ADDRESS/DATA BUS TIMING

(TA = 0°C to +70°C; VCC = 5V ±10%)

#

PARAMETER

SYMBOL

MIN

MAX

UNITS

40

Delay to Byte-Wide Address Valid from

tCE1LPA

30

ns

,

, or

Low During Op Code

CE1

CE2

CE1N

Fetch

41

Pulse Width of

1-4,

1-4 or

tCEPW

4tCLK - 35

ns

CE

PE

CE1N

Byte-Wide Address Hold After

,

, or

42

CE1

CE2

tCE1HPA

2tCLK - 20

ns

CE1N High During Op Code Fetch

Byte-Wide Data Setup to

,

, or

43

CE1

CE2

CE1N

tOVCE1H

1tCLK + 40

ns

High During Op Code Fetch

Byte-Wide Data Hold After

,

or

44

CE1

CE2

tCE1HOV

0

ns

CE1N High During Op Code Fetch

Byte-Wide Address Hold After

1-4,

45

CE

tCEHDA

4tCLK - 30

ns

PE 1-4, or CE1N High During MOVX

46

Delay from Byte-Wide Address Valid

tCELDA

4tCLK - 35

ns

CE 1-4, PE 1-4, or CE1N Low During MOVX

Byte-Wide Data Setup to

1-4,

1-4, or

47

CE

PE

tDACEH

1tCLK + 40

ns

CE1N High During MOVX (read)

Byte-Wide Data Hold After

1 - 4,

48

CE

tCEHDV

0

ns

PE 1-4, or CE1N High During MOVX (read)

Byte-Wide Address Valid to R/

Active

49

W

tAVRWL

3tCLK - 35

ns

During MOVX (write)

Delay from R/

Low to Valid Data Out

50

W

tRWLDV

20

ns

During MOVX (write)

Valid Data-Out Hold Time from

1-4,

51

CE

tCEHDV

1tCLK - 15

ns

PE 1-4, or CE1N High

52

Valid Data-Out Hold Time from R/

High

tRWHDV

0

ns

W

53

Write Pulse Width (R/

Low Time)

tRWLPW

6tCLK - 20

ns

W

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