Maxtor 90750D3, 91024D4, 91280D5, 91536D6, 91792D7, 92048D8 Ultra DMA Timing

AT INTERFACE DESCRIPTION

5 – 26

Ultra DMA Timing

TIMING PARAMETERS (all times in nanoseconds) MODE 0 MODE 1 MODE 2

MIN MAX MIN MAX MIN MAX

tCYC Cycle Time (from STROBE edge to STROBE edge) 114 75 55

t2CYC Two cycle time (from rising edge to next rising edge or

from falling edge to next falling edge of STROBE)235 156 117

tDS Data setup time (at recipient) 15 10 770

tDH Data hold time (at recipient) 555

tDVS Data valid setup time at sender (time from data bus being

valid until STROBE edge) 70 48 34 5

tDVH Data valid hold time at sender (time from STROBE edge

until data may go invalid) 66620

tFS First STROBE (time for device to send first STROBE) 0230 0200 0 170

tLI Limited interlock time (time allowed between an action by

one agent, either host or device, and the following action

by the other agent) 0 150 0 150 0 150

tMLI Interlock time with minimum 20 20 20

tUI Unlimited interlock time 000

tAZ Maximum time allowed for outputs to release 10 10 10

tZAH Minimum delay time required for output drivers turning on

(from released state)

20 20 20

tZAD 000

tENV Envelope time (all control signal transitions are within the

DMACK envelope by this much time) 20 70 20 70 20 70

tSR STROBE to DMARDY (response time to ensure the

synchronous pause case when the recipient is pausing) 50 30 20

tRFS Ready-to-final-STROBE time (no more STROBE edges may

be sent this long after receiving DMARDY- negation) 75 60 50

tRP Ready-to-pause time (time until a recipient may assume

that the sender has paused after negation of DMARDY-) 160 125 100

tIORDYZ Pull-up time before allowing IORDY to be released 20 20 20

tZIORDY Minimum time device shall wait before driving IORDY 000

tACK Setup and hold times before assertion and negation of

DMACK- 20 20 20

tSS Time from STROBE edge to STOP assertion when the

sender is stopping

50 50 50

DMARQ

(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

DD(15:0)

tZAD

DA0, DA1, DA2,

CS0-, CS1-

tUI

tZAD

tACK

tACK

tENV

tENV

tZIORDY

tFS

tFS

tVDS

tAZ tDVH

tACK

Figure 5 - 4

Initiating an Ultra DMA Data In Burst

Contents

Main DiamondMax Plus 5120 92048D8, 91792D7, 91536D6, 91280D5, 91024D4 and 90750D3 Page Page Contents Section 1 Introduction Section 2 Product Description Section 3 Product Specifications Section 4 Handling and Installation Section 5 AT Interface Description Section 6 Host Software Interface Section 7 Interface Commands Section 8 Service and Support Glossary Figures Figure Title Page SECTION 1 Introduction Maxtor Corporation Manual Organization Abbreviations Conventions SECTION 2 Product Description DiamondMax Plus 5120 Key Features Product Features Functional / Interface Page Cache Management Major HDA Components Figure 2-1 PCBA Jumper Location and Configuration 4092 Cylinder Limitation Subsystem Configuration Jumper Location/Configuration PRODUCT SPECIFICATIONS 3 1 Product Specifications Drive Configuration Performance Specifications Models and Capacities LEDOM 8D840297D297196D635195D082194D420193D05709 yticapaCdettamroF Physical Dimensions Figure 3 - 1 Outline and Mounting Dimensions Power Requirements Power Mode Definitions EPA Energy Star Compliance Environmental Limits Reliability Specifications Shock and Vibration EMC/EMI Safety Regulatory Compliance SECTION 4 Handling and Installation Pre-formatted Drive Important Notice Hard Drive Handling Precautions Electro-Static Discharge (ESD) Page Page 4 15 1 IMPORTANT PLEASE READ! Handling Precautions P ( H H H 3 Identifying IDE Devices on the Interface Jumper Settings 2 System Hardware Requirements 4 Installing 5.25-inch Mounting Brackets and Rails Installing in a Device Bay Systems Using Cable Select Relationship to Other IDE Devices 5 and Power Cables 6 4 19 7 Setting the BIOS (CMOS) BIOS (CMOS) Parameters 4 20 8 4 21 9 5 22 SECTION 5 AT Interface Description Interface Connector Figure 5-1 Data Connector Pin Description Summary 5 23 Pin Description Table 5 24 PIO Timing Figure 5 - 2 PIO Data Transfer To/From Device 5 25 DMA Timing Figure 5 - 3 Multi-word DMA Data Transfer 5 26 Ultra DMA Timing Figure 5 - 4 Initiating an Ultra DMA Data In Burst 5 27 Figure 5 - 5 Sustained Ultra DMA Data In Burst Figure 5 - 6 Host Pausing an Ultra DMA Data In Burst 5 28 Figure 5 - 7 Device Terminating an Ultra DMA Data In Burst Figure 5 - 8 Host Terminating an Ultra DMA Data In Burst 5 29 Figure 5 - 9 Initiating an Ultra DMA Data Out Burst Figure 5 - 10 Sustained Ultra DMA Data Out Burst 5 30 Figure 5 - 11 Device Pausing an Ultra DMA Data Out Burst Figure 5 - 12 Host Terminating an Ultra DMA Data Out Burst 5 31 Figure 5 - 13 Device Terminating an Ultra DMA Data Out Burst SECTION 6 Host Software Interface Task File Registers Page Command Register HOST SOFTWARE INTERFACE Summary 6 4 Control Diagnostic Registers Reset and Interrupt Handling SECTION 7 Interface Commands Read Commands Page Write Commands Page Set Feature Commands Power Mode Commands Page Initialization Commands INTERFACE COMMANDS 7 10 INTERFACE COMMANDS 7 11 Page Seek, Format and Diagnostic Commands S.M.A.R.T. Command Set SECTION 8 Service and Support Service Policy No Quibble Service Support Page GL 1 GLOSSARY Glossary A B C GL 2 D E F GL 3 G H I J K M N O P GL 5 R S GL 6 T U V W