•Parallel input connector port Signal allocation (Signal : Nibble)
Pin No. Return |
| Signal | From/To | Function | ||||
| pin No. |
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1 | 19 |
| HostClk | PC/DP | High | |||
2 - 9 20 - 27 | Unknown | PC/DP | Unknown | |||||
10 | 28 |
| PrtClk | PC/DP | Sends data in “Low” when HostBusy is “Low”. After HostBusy | |||
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| turns “High”, this signal becomes “High”. |
11 | 29 |
| PtrBusy | PC/DP | Data4, Data8(MSB) | |||
12 |
| AckDataReq | PC/DP | Data3, Data7 | ||||
13 |
|
| Xflag |
| Data2, Data6 | |||
14 |
| HostBusy | PC/DP | High: DP is on BUSY status. | ||||
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| Low: DP can send data. |
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16•17 |
|
| GND |
| Earth | |||
18 |
|
| High | PC/DP | PeripheralLogicHigh | |||
19 - 30 |
|
| GND |
| Earth | |||
31 | 16 |
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| PC/DP | Clears sending data to this unit. (Low) Incoming pulse width |
|
| Init | ||||||
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| should be 100∝ s minimum. |
32 |
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| PC/DP | Data1(LSB), Data5 | ||
| DataAvail | |||||||
15• |
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| NC |
| Unused | ||
33 - 35 |
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36 |
| 1284 Active | PC/DP | Becomes “High” when DP requests each mode of IEEE1284. | ||||
21
