National Instruments DAQ S - page 137

Chapter 11 Triggering

© National Instruments Corporation 11-5 NI 6124/6154 User Manual

For the trigger to assert, the signal must first be below the low

threshold, then go above the high threshold. The trigger stays

asserted until the signal returns below the low threshold. The

output of the trigger detection circuitry is the internal Analog

Comparison Event signal, as shown in Figure11-5.

Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example

– Analog Edge Trigger with Hysteresis (Falling Slope)—When

using hysteresis with a falling slope, you specify a trigger level

and amount of hysteresis. The low threshold is the trigger level;

the high threshold is the trigger level plus the hysteresis.

For the trigger to assert, the signal must first be above the high

threshold, then go below the low threshold. The trigger stays

asserted until the signal returns above the high threshold. The

output of the trigger detection circuitry is the internal Analog

Comparison Event signal, as shown in Figure11-6.

Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example

Analog Comparison Event

Hysteresis

High threshold

(Level)

Low threshold

(Level – Hysteresis)

First signal must go

below low threshold

Then signal must

go above high threshold before

Analog Comparison Event asserts

Analog Comparison Event

Hysteresis

High threshold

(Level + Hysteresis)

Low threshold

(Level)

First signal must go

above high threshold

Then signal must go below low threshold

before Analog Comparison Event asserts

Contents

Main Page Important Information Warranty Copyright Trademarks Patents Compliance Compliance with FCC/Canada Radio Frequency Interference Regulations Determining FCC Class FCC/DOC Warnings Class A Contents Chapter 5 Analog Output Chapter 6 Digital I/O Chapter 7 Counters Page Chapter 8 Programmable Function Interfaces (PFI) Chapter 9 Digital Routing and Clock Generation Page About This Manual Conventions Related Documentation NI-DAQmx for Windows LabVIEW LabWindows/CVI Measurement Studio ANSI C without NI Application Software .NET Languages without NI Application Software Device Documentation and Specifications Training Courses Technical Support on the Web Getting Started Installing NI-DAQmx Installing Other Software Installing the Hardware Device Self-Calibration Page DAQ System Overview DAQ Hardware DAQ-STC2 Calibration Circuitry Internal or Self-Calibration External Calibration Signal Conditioning Sensors and Transducers Programming Devices in Software I/O Connector NI 6124 I/O Connector Signal Descriptions NI 6154 I/O Connector Signal Descriptions (NI 6154 Only) Table3 -2 describes the signals found on the NI 6154 I/O connector. For more information about these signals, refer to the NI 6154 Specifications. Table 3-2. NI 6154 I/O Connector Signal Descriptions Table 3-1. NI 6124 Device Signal Descriptions (Continued) +5 V Power Source Analog Input Figure 4-2. Isolated S Series Analog Input Block Diagram Figure 4-1. Non-Isolated S Series Analog Input Block Diagram Analog Input Terminal Configuration Input Polarity and Range Working Voltage Range AI Data Acquisition Methods Page Analog Input Triggering Connecting Analog Input Signals Types of Signal Sources Differential Connections for Ground-Referenced Signal Sources Figure 4-3. Differential Connection for Ground-Referenced Signals on Non-Isolated Devices Figure 4-4. Differential Connection for Ground-Referenced Signals on Isolated Devices Common-Mode Signal Rejection Considerations Differential Connections for Non-Referenced or Floating Signal Sources DC-Coupled AC-Coupled Field Wiring Considerations Minimizing Drift in Differential Mode Analog Input Timing Signals AI Sample Clock Signal Routing AI Sample Clock Signal to an Output Other Timing Requirements AI Sample Clock Timebase Signal AI Convert Clock Signal Routing AI Convert Clock Signal to an Output AI Convert Clock Timebase Signal AI Hold Complete Event Signal AI Start Trigger Signal Routing AI Start Trigger to an Output Terminal AI Reference Trigger Signal Routing AI Reference Trigger Signal to an Output Getting Started with AI Applications in Software Analog Output Minimizing Glitches on the Output Signal AO Data Generation Methods Page Analog Output Triggering Connecting Analog Output Signals Figure 5-3 shows how AO 0 and AO 1 are wired on a non-isolated S Series device. Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices Figure 5-4. Analog Output Connections for Isolated S Series Devices Figure 5-4 shows how AO 0 is wired on an isolated S Series device. Waveform Generation Timing Signals AO Sample Clock Signal Routing AO Sample Clock Signal to an Output Other Timing Requirements AO Sample Clock Timebase Signal AO Start Trigger Signal Routing AO Start Trigger Signal to an Output AO Pause Trigger Signal Getting Started with AO Applications in Software Digital I/O Digital I/O for Non-Isolated Devices Static DIO for Non-Isolated Devices Digital Waveform Triggering for Non-Isolated Devices Digital Waveform Acquisition for Non-Isolated Devices DI Sample Clock Signal Using an Internal Source Using an External Source Routing DI Sample Clock to an Output Terminal Digital Waveform Generation for Non-Isolated Devices DO Sample Clock Signal Using an Internal Source Using an External Source Routing DO Sample Clock to an Output Terminal I/O Protection for Non-Isolated Devices Programmable Power-Up States for Non-Isolated Devices DI Change Detection for Non-Isolated Devices DI Change Detection Applications for Non-Isolated Devices Connecting Digital I/O Signals on Non-Isolated Devices Getting Started with DIO Applications in Software on Non-Isolated Devices Digital I/O for Isolated Devices Static DIO for Isolated Devices I/O Protection for Isolated Devices Connecting Digital I/O Signals on Isolated Devices Getting Started with DIO Applications in Software on Isolated Devices Counters Figure 7-1. SSeries Counters Counter Input Applications Counting Edges Single Point (On-Demand) Edge Counting Buffered (Sample Clock) Edge Counting Controlling the Direction of Counting Pulse-Width Measurement Single Pulse-Width Measurement Buffered Pulse-Width Measurement Period Measurement Single Period Measurement Buffered Period Measurement Semi-Period Measurement Single Semi-Period Measurement Buffered Semi-Period Measurement Frequency Measurement Page Page Choosing a Method for Measuring Frequency Page Position Measurement Measurements Using Quadrature Encoders Channel Z Behavior Measurements Using Two Pulse Encoders Buffered (Sample Clock) Position Measurement Two-Signal Edge-Separation Measurement Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Counter Output Applications Simple Pulse Generation Single Pulse Generation Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation Pulse Train Generation Continuous Pulse Train Generation Finite Pulse Train Generation Frequency Generation Using the Frequency Generator Frequency Division Pulse Generation for ETS Counter Timing Signals Counter n Source Signal Routing a Signal to Counter n Source Routing Counter n Source to an Output Terminal Counter n Gate Signal Routing a Signal to Counter n Gate Routing Counter n Gate to an Output Terminal Counter n Aux Signal Routing a Signal to Counter n Aux Counter n A, Counter n B, and Counter n Z Signals Routing Signals to A, B, and Z Counter Inputs Routing Counter n Z Signal to an Output Terminal Counter n Up_Down Signal Counter n HW Arm Signal Routing Signals to Counter n HW Arm Input Counter n Internal Output and Counter n TC Signals Routing Counter n Internal Output to an Output Default Counter/Timer Pinouts Counter Triggering Other Counter Features Cascading Counters Counter Filters Prescaling Duplicate Count Prevention Example Application That Works Correctly (No Duplicate Counting) Example Application That Works Incorrectly (Duplicate Counting) Example Application That Prevents Duplicate Count When To Use Duplicate Count Prevention Enabling Duplicate Count Prevention in NI-DAQmx Synchronization Modes 80 MHz Source Mode Other Internal Source Mode External Source Mode Programmable Function Interfaces (PFI) PFI for Non-Isolated Devices PFI for Isolated Devices Page Using PFI Terminals as Timing Input Signals Exporting Timing Output Signals Using PFI Terminals Using PFI Terminals as Static Digital Inputs and Outputs Connecting PFI Input Signals PFI Filters Page I/O Protection Programmable Power-Up States Page Digital Routing and Clock Generation Clock Routing 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase External Reference Clock 10 MHz Reference Clock Synchronizing Multiple Devices Real-Time System Integration (RTSI) RTSI Connector Pinout Using RTSI as Outputs Using RTSI Terminals as Timing Input Signals RTSI Filters Page PXI Clock and Trigger Signals PXI_CLK10 PXI Triggers PXI_STAR Trigger PXI_STAR Filters Routing Signals in Software Bus Interface MITE and DAQ-PnP PXI Considerations PXI Clock and Trigger Signals PXI Express Data Transfer Methods Changing Data Transfer Methods between DMA and IRQ Triggering Triggering with a Digital Source Triggering with an Analog Source Analog Input Channel Analog Trigger Actions Analog Trigger Types Page Page Analog Trigger Accuracy A Device-Specific Information NI 6124 NI 6124 Analog Output NI 6124/6154 User Manual A-2 ni.com Note The AO channels do not have analog or digital filtering hardware and do produce NI 6124 I/O Connector Pinout Figure A-1 shows the pin assignments for the 68-pin connector on the NI6 124. Page NI 6124/6154 User Manual A-4 ni.com NI 6124 Block Diagram Figure A-2 shows the NI 6124 block diagram. ASIC ni.com. Figure A-2. NI 6124 Block Diagram Using BNCs Using Screw Terminals Using SSR or ER Digital Signal Conditioning Custom Cabling/Connectors Options NI 6124 Specifications NI 6154 NI 6154 Analog Output NI 6154 I/O Connector Pinout Figure A-3 shows the pin assignments for the 37-pin I/O connector on the NI 6154. Figure A-3. NI 6154 Pinout Table A-2. NI6154 Device Default NI-DAQmx Counter/Timer Pins Page NI 6124/6154 User Manual A-10 ni.com NI 6154 Block Diagram PCI Connector 37-Pin D-SUB Connector Figure A-4 shows the NI 6154 block diagram. Figure A-4. NI 6154 Block Diagram NI 6154 Isolation and Digital Isolators Digital Isolation Benefits of an Isolated DAQ Device NI 6154 Specifications B Technical Support and Professional Services Page Glossary Symbols A B C Page D E F G H I L M N P Q R S T V Page Index Numerics A B C D E F G H I K L N O P Q R S T U W X