Chapter 6 Digital I/O
© National Instruments Corporation 6-5 NI 6124/6154 User Manual
•PXI_STAR
• Analog Comparison Event (an analog trigger)
You can sample data on the rising or falling edge of DI Sample Clock.

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock out to any PFI terminal. The PFI circuitry
inverts the polarity of DI Sample Clock before driving the PFI terminal.
Digital Waveform Generation for Non-Isolated Devices
(NI 6124 Only) You can generate digital waveforms on the Port 0 DIO lines.
The DO waveform generation FIFO stores the digital samples. These
SS eries devices have a DMA controller dedicated to moving data from the
system memory to the DO waveform generation FIFO. The DAQ device
moves samples from the FIFO to the DIO terminals on each rising or falling
edge of a clock signal, DO Sample Clock. You can configure each DIO
signal to be an input, a static output, or a digital waveform generation
output.
The FIFO supports a retransmit mode. In the retransmit mode, after all the
samples in the FIFO have been clocked out, the FIFO begins outputting all
of the samples again in the same order. For example, if the FIFO contains
five samples, the pattern generated consists of sample #1, #2, #3, #4, #5,
#1, #2, #3, #4, #5, #1, and so on.
DO Sample Clock Signal
(NI 6124 Only) Use the DO Sample Clock (do/SampleClock) signal to update
the DO terminals with the next sample from the DO waveform generation
FIFO. These S Series devices do not have the ability to divide down a
timebase to produce an internal DO Sample Clock for digital waveform
generation. Therefore, you must route an external signal or one of many
internal signals from another subsystem to be the DO Sample Clock. For
example, you can correlate digital and analog samples in time by sharing
your AI Sample Clock or AO Sample Clock as the source of your
DO Sample Clock. To generate digital data independent of an AI, AO,
or DIoperatio n, you can configure a counter to generate the desired
DO Sample Clock or use an external signal as the source of the clock.
If the DAQ device receives a DO Sample Clock when the FIFO is empty,
the DAQ device reports an underflow error to the host software.