Index
PCI-MXI-2 for Linux I-8 ni.com
parts locator diagram (figure), 4-2
VMEbus A16 base address, 4-3
VME-MXI-2 intermodule
signaling, 4-4
connecting MXIbus cable, 4-11
default settings
Configuration Editor settings
(table),1-13
hardware description, 1-4
installation, 4-10
quick start installation, 1-7
specifications
electrical, A-11
environmental, A-10
MXIbus capability descriptions, A-8
performance, A-11
physical, A-10
requirements, A-10
VMEbus capability codes, A-8
VXI shared RAM options, 6-6
advanced shared RAM settings, 6-8
illustration, 6-8
caution, 6-10
enable byte swapping, 6-9
lower half window and upper half
window, 6-7
memory select, 6-9
shared RAM pool, 6-7
VXI/VME shared RAM size, 6-7
window mapping, 6-9
VXI/VME automatic retry feature, 6-25
VXI/VME extender kit
hardware description, 1-4
introduction, 1-1
MXI-2 description, 1-3
overview, 1-3
requirements for getting started, 1-3
software description, 1-5
VXI/VME-MXI-2 Configuration Editor
A16 write post and A24/A32 write
post, 6-21
address space and requested
memory,6-20
and RESMAN, 6-19
default settings (table), 1-13
illustration, 6-20
interlocked mode, 6-22
LA selection and logical address, 6-20
MXI bus configuration options
advanced MXI settings, 6-28
illustration, 6-28
MXI auto retry, 6-28
MXI bus system controller, 6-27
MXI bus timeout value (BTO, 6-27
MXI CLK10 signal, 6-29
caution statement, 6-29
MXI fair requester, 6-29
parity checking, 6-29
transfer limit, 6-29
VXI/VME bus options, 6-23
advanced VXI settings, 6-24
illustration, 6-25
VXI/VME bus timeout value
(BTO), 6-24
arbiter timeout, 6-27
arbiter type, 6-26
request level, 6-26
transfer limit, 6-25
VXI/VME auto retry, 6-25
VXI/VME fair requester, 6-26
VXI/VME-MXI-2
selection dialog box (figure), 6-19
VXI/VME-MXI-2 (note), 6-19
VXIbus CLK10 routing, 3-8
CLK10 generation (figure), 3-9
SMB CLK10 settings (figure), 3-9, 3-11
VXIbus local bus, 3-7
VXIbus logical address, 3-3
See also logical address
VXIbus logical address. See logical address
VXIbus Slot 0/non-Slot 0, 3-5