National Instruments NI 6232, NI 6233 PXI Considerations

Chapter 11 Bus Interface

NI 6232/6233 User Manual 11-2 ni.com

Each DMA controller supports packing and unpacking of data through the

FIFOs to connect different size devices and optimize PCI bus utilization

and automatically handles unaligned memory buffers.

PXI Considerations

Note PXI clock and trigger signals are only available on PXI devices. Other devices use

RTSI.

PXI Clock and Trigger Signals

Refer to the PXI_CLK10, PXI Triggers, PXI_STAR Trigger, and

PXI_STAR Filters sections of Chapter 10, Digital Routing and Clock

Generation, for more information on PXI clock and trigger signals.

PXI and PXI Express

NI PXI-6232/6233 modules can be installed in any PXI chassis and most

slots of PXI Express chassis.

PXI specifications are developed by the PXI System Alliance

(www.pxisa.org). Using the terminology of the PXI specifications,

NI PXI-6232/6233 devices are 3U Hybrid Slot-Compatible PXI-1

Peripheral Modules.

3U designates devices that are 100 mm tall (as opposed to the taller 6U

modules).

Hybrid slot-compatible defines where the device can be installed.

PXI-6232/6233 devices can be installed in the following chassis and slots:

•PXI chassis—PXI-6232/6233 devices can be installed in any

peripheral slot of a PXI chassis.

•PXI Express chassis—PXI-6232/6233 devices can be installed in the

following PXI Express chassis slots:

–PXI-1 slots—Accepts all PXI modules

–PXI hybrid slots—Accepts PXI or PXI Express modules.

PXI-1 devices use PCI signaling to communicate to the host controller (as

opposed to PCI Express signaling).

Peripheral devices are installed in peripheral slots and are not system

controllers.

Contents

Main Page Important Information Warranty Copyright Trademarks Patents Page Compliance Compliance with FCC/Canada Radio Frequency Interference Regulations Determining FCC Class FCC/DOC Warnings Class A Contents About This Manual Chapter 1 Getting Started Chapter 2 DAQ System Overview Chapter 3 Connector Information Chapter 4 Analog Input Chapter 5 Analog Output Chapter 6 Digital Input and Output Chapter 7 Counters Page Chapter 8 PFI Chapter 9 Isolation and Digital Isolators Chapter 10 Digital Routing and Clock Generation Page About This Manual Conventions Related Documentation NI-DAQ NI-DAQmx for Linux NI-DAQmx Base LabVIEW LabWindows/CVI Measurement Studio ANSI C without NI Application Software .NET Languages without NI Application Software Device Documentation and Specifications Training Courses Technical Support on the Web Getting Started Installing NI-DAQmx Installing Other Software Installing the Hardware Device Pinouts Page DAQ System Overview DAQ Hardware DAQ-STC2 Calibration Circuitry Sensors and Transducers Cables and Accessories Custom Cabling Programming Devices in Software Connector Information I/O Connector Signal Descriptions Table 3-1. I/O Connector Signals (Continued) Page Analog Input Analog Input Circuitry Analog Input Range Analog Input Ground-Reference Settings (10 V (10 V)) 216 = 305 mV Page Configuring AI Ground-Reference Settings in Software Multichannel Scanning Considerations Use Low Impedance Sources Use Short High-Quality Cabling Carefully Choose the Channel Scanning Order Avoid Switching from a Large to a Small Input Range Insert Grounded Channel between Signal Channels Minimize Voltage Step between Adjacent Channels Avoid Scanning Faster Than Necessary Example 1 Example 2 Analog Input Data Acquisition Methods Software-Timed Acquisitions Hardware-Timed Acquisitions Buffered Non-Buffered Analog Input Triggering Connecting Analog Voltage Input Signals Types of Signal Sources Floating Signal Sources Ground-Referenced Signal Sources Differential Connection Considerations Differential Connections for Ground-Referenced Signal Sources Differential Input Biasing Differential Connections for Non-Referenced or Floating Signal Sources Single-Ended Connection Considerations Single-Ended Connections for Floating or Grounded Signal Sources Field Wiring Considerations Analog Input Timing Signals Page Page AI Sample Clock Signal Using an Internal Source Using an External Source Routing AI Sample Clock Signal to an Output Other Timing Requirements AI Sample Clock Timebase Signal AI Convert Clock Signal Using an Internal Source Using an External Source Routing AI Convert Clock Signal to an Output Using a Delay from Sample Clock to Convert Clock Other Timing Requirements AI Convert Clock Timebase Signal AI Hold Complete Event Signal AI Start Trigger Signal Routing AI Start Trigger to an Output Terminal AI Reference Trigger Signal Routing AI Reference Trigger Signal to an Output AI Pause Trigger Signal Routing AI Pause Trigger Signal to an Output Getting Started with AI Applications in Software Analog Output Analog Output Circuitry Minimizing Glitches on the Output Signal Analog Output Data Generation Methods Software-Timed Generations Hardware-Timed Generations Non-Buffered Buffered Analog Output Triggering Connecting Analog Voltage Output Signals Figure 5-2. Analog Output Connections Analog Output Timing Signals Figure 5-3 summarizes all of the timing options provided by the analog output timing engine. AO Start Trigger Signal Routing AO Start Trigger Signal to an Output AO Pause Trigger Signal Routing AO Pause Trigger Signal to an Output AO Sample Clock Signal Page AO Sample Clock Timebase Signal Getting Started with AO Applications in Software Page Digital Input and Output I/O Protection Programmable Power-Up States Connecting Digital I/O Signals Logic Conventions Getting Started with DIO Applications in Software Counters Figure 7-1. M Series Counters Counter Input Applications Counting Edges Single Point (On-Demand) Edge Counting Buffered (Sample Clock) Edge Counting Non-Cumulative Buffered Edge Counting Controlling the Direction of Counting Pulse-Width Measurement Single Pulse-Width Measurement Buffered Pulse-Width Measurement Period Measurement Single Period Measurement Buffered Period Measurement Semi-Period Measurement Single Semi-Period Measurement Buffered Semi-Period Measurement Frequency Measurement Method 1Measure Low Frequency with One Counter Method 1bMeasure Low Frequency with One Counter (Averaged) Figure 7-12. Method 1b Method 2Measure High Frequency with Two Counters Method 3Measure Large Range of Frequencies Using Two Counters Choosing a Method for Measuring Frequency Page Position Measurement Measurements Using Quadrature Encoders X1 Encoding X2 Encoding X4 Encoding Channel Z Behavior Measurements Using Two Pulse Encoders Two-Signal Edge-Separation Measurement Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Counter Output Applications Simple Pulse Generation Single Pulse Generation Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation Pulse Train Generation Continuous Pulse Train Generation Frequency Generation Using the Frequency Generator Frequency Division Pulse Generation for ETS Counter Timing Signals Counter n Source Signal Routing a Signal to Counter n Source Routing Counter n Source to an Output Terminal Counter n Gate Signal Routing a Signal to Counter n Gate Routing Counter n Gate to an Output Terminal Counter n Aux Signal Routing a Signal to Counter n Aux Counter n A, Counter n B, and Counter n Z Signals Routing Signals to A, B, and Z Counter Inputs Routing Counter n Z Signal to an Output Terminal Counter n Up_Down Signal Counter n HW Arm Signal Routing Signals to Counter n HW Arm Input Counter n Internal Output and Counter n TC Signals Routing Counter n Internal Output to an Output Frequency Output Signal Default Counter Terminals Counter Triggering Arm Start Trigger Start Trigger Pause Trigger Other Counter Features Cascading Counters Counter Filters Prescaling Duplicate Count Prevention Duplicate Count Prevention Example Duplicate Count Example Example Application That Prevents Duplicate Count When To Use Duplicate Count Prevention Enabling Duplicate Count Prevention in NI-DAQmx Synchronization Modes 80 MHz Source Mode Other Internal Source Mode External Source Mode PFI Using PFI Terminals as Timing Input Signals Exporting Timing Output Signals Using PFI Terminals Using PFI Terminals as Static Digital Inputs and Outputs Connecting PFI Input Signals PFI Filters I/O Protection Programmable Power-Up States Connecting Digital I/O Signals Figure 8-5. NI 6232 Digital I/O Connections (DO Source) Page Isolation and Digital Isolators Digital Isolation Benefits of an Isolated DAQ Device Digital Routing and Clock Generation Clock Routing 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase External Reference Clock 10 MHz Reference Clock Synchronizing Multiple Devices Real-Time System Integration Bus (RTSI) RTSI Connector Pinout Using RTSI as Outputs Using RTSI Terminals as Timing Input Signals RTSI Filters Page PXI Clock and Trigger Signals PXI_CLK10 PXI Triggers PXI_STAR Trigger PXI_STAR Filters Page Bus Interface DMA Controllers PXI Considerations PXI Clock and Trigger Signals PXI and PXI Express Using PXI with CompactPCI Data Transfer Methods Direct Memory Access (DMA) Interrupt Request (IRQ) Programmed I/O Changing Data Transfer Methods between DMA and IRQ Triggering Triggering with a Digital Source Page A Device-Specific Information NI 6232 NI 6232 Pinout Figure A-1. NI 6232 Pinout Table A-1. NI 6232 Device Default NI-DAQmx Counter/Timer Pins NI 6232 Specifications NI 6232 Accessory and Cabling Options Screw Terminal RTSI NI 6233 Figure A-2. NI 6233 Pinout Table A-2. NI 6233 Device Default NI-DAQmx Counter/Timer Pins NI 6233 Specifications NI 6233 Accessory and Cabling Options Screw Terminal RTSI Page B Troubleshooting Analog Input Page Analog Output Counters C Technical Support and Professional Services Page Glossary Numbers/Symbols A Page B C Page D Page E F G H I Page K L M N O P Q R S Page T U V W Index Symbols Numerics A B C D E F G H I K L M N O P Q R S T U