Chapter 3 Hardware Overview
NI PXIe-6672 User Manual 3-12 ni.com
Table3-4 summarizes the sources and destinations of the NI PXIe-6672.
The destinations are listed in the horizontal heading row, and the sources
are listed in the column at the far left. A ✓ in a cell indicates that the source
and destination combination defined by that cell is a valid routing
combination.
Using Front Panel PFIs As Inputs
The front-panel PFIs can receive external signals from 0 to +5V. They can
be terminated programmatically with 50Ω resistances to match the cable
impedance and minimize reflections.
Note Terminating the signals with a 50Ω resistance is recommended when the source is
another NI PXIe-6672 or any other source with a 50 Ω output.
The voltage thresholds for the front-panel PFI inputs are programmable.
The input signal is generated by comparing the input voltage on the
Table 3-4. Sources and Destinations for NI PXIe-6672 Signal Routing Operations
Sources
Destinations
Front Panel Backplane Onboard
Front Panel
CLKOUT PFI<0..5> PXI_
CLK10_IN
PXI_Star
Trigger
<0..16>
PXI TRIG
<0..7>
TCXO
Reference
PLL
CLKIN ✓*✓*✓ ✓ ✓*✓
PFI<0..5> ✓ ✓ ✓
Backplane
PXI_ CLK10 ✓ ✓†✓†✓†
PXI_STAR
<0..16>
✓ ✓ ✓
PXI TRIG
<0..7>
✓ ✓ ✓
Onboard
TCXO ✓ ✓*✓ ✓*✓*
DDS ✓ ✓†✓†✓†
Global
Software
Trigger
✓ ✓ ✓
* Can be accomplished in two stages by routing source to PXI_CLK10_IN, replacing PXI_CLK10 with PXI_CLK10_IN
(occurs automatically in most chassis), and then routing PXI_CLK10 to the destination. The source must be 10 MHz.
† Routing PXI_CLK10 or DDS to PFI, PXI_Star, or PXI_Trigger is accomplished by setting PXI_CLK10 or DDS to be the
synchronization clock (NI-Sync Property Node) and then routing the synchronization clock as the source.