National Instruments NI PXIe-6672 P

Glossary

PCI peripheral component interconnect—a high-performance expansion bus

architecture originally developed by Intel to replace ISA and EISA. It is

achieving widespread acceptance as a standard for PCs and work-stations;

it offers a theoretical maximum transfer rate of 132 Mbytes/s.

PCI Express peripheral component interconnect express—a high-performance

expansion bus architecture that expands on and doubles the data transfer

rates of original PCI. PCI Express is a two-way, serial connection that

carries data in packets along two pairs of point-to-point data lanes,

compared to the single parallel data bus of traditional PCI that routes data

at a set rate. Initial bit rates for PCI Express reach 2.5Gb/s per lane

direction, which equate to data transfer rates of approximately

200 Mbytes/s.

PFI programmable function interface

PLL phase-locked loop

precision The measure of the stability of an instrument and its capability to give the

same measurement over and over again for the same input signal.

propagation delay The amount of time required for a signal to pass through a circuit.

PXI A rugged, open system for modular instrumentation based on CompactPCI,

with special mechanical, electrical, and software features. The PXIbus

standard was originally developed by National Instruments in 1997, and

is now managed by the PXIbus Systems Alliance.

PXI Express An open system for modular instrumentation based on PXI and

CompactPCI Express. PXI Express enhances system timing and software

frameworks while preserving backward compatibility with PXI. The

system controller slot is capable of supporting up to a x16 PCI Express link,

plus a x8 link, providing a total of 6 GB/s bandwidth to the PXI backplane,

which is more than 45 times improvement upon PXI backplane throughput

PXI star A special set of trigger lines in the PXI backplane for high-accuracy device

synchronization with minimal latencies on each PXI slot.

PXI_Trig/PXI_Star

synchronization clock

The clock signal that is used to synchronize the PXI triggers or PXI_STAR

triggers on an NIPXIe-667 2.