National Instruments NI PXIe-6672 Using Front Panel PFIs As Outputs

Chapter 3 Hardware Overview

PFIc onnectors to the voltage output of software-programmable DACs.

The thresholds for the PFI lines are individually programmable, which is

useful if you are importing signals from multiple sources with different

voltage swings. Thef ront panel PFI inputs can be routed to any PXI_Star

triggers, PXI triggers, or other front panel PFI outputs.

Using Front Panel PFIs As Outputs

The front panel PFI outputs are +3.3 V drivers with 50 Ω output

impedance. The outputs can drive 50 Ω loads, such as a 50 Ω coaxial cable

with a 50 Ω receiver. This cable configuration is the recommended setup to

minimize reflections. With this configuration, the receiver sees a single

+1.6 V step—a +3.3 V step split across the 50 Ω resistors at the source and

the destination.

You also can drive a 50Ω cable with a high-impedance load. The

destination sees a single step to +3.3 V, but the source sees a reflection.

This cable configuration is acceptable for low-frequency signals or short

cables. You can select the signal source from the front panel triggers

(PFI <0..5>), the PXI star triggers, the PXI triggers, or the synchronization

clock (PXI_CLK10, the DDS clock, or PFI 0). The synchronization clock

concept is explained in more detail in the Choosing the Type of Routing

section.

You can independently select the output signal source for each PFI line

from one of the following sources:

• Another PFI<0..5>

• PXI triggers<0..7> (PXI_TRIG <0..7>)

• PXI_STAR<0..16>

• Global software trigger

• PFI synchronization clock

The PFI synchronization clock may be any of the following signals:

• DDS clock

•PXI_CLK10

• PFI0 Input

• Any of the previously listed signals divided by the first frequency

divider (2n,up to 512)

• Any of the previously listed signals divided by the second frequency

divider (2m,up to 512)