Chapter 9 Counters
| Table |
|
|
t0 | At t0, the counter is armed. No measurements are taken until the counter is armed. |
|
|
t1 | The rising edge of Gate indicates the beginning of the first period to measure. The |
| counter begins counting rising edges of Source. |
|
|
t2 | The rising edge of the Sample Clock indicates that the USB M Series device should |
| store the result of the measurement of the current period when the period ends. |
|
|
t3 | The rising edge of Gate indicates the end of the first period. The USB M Series device |
| stores the counter value in the buffer. |
|
|
t4 | The rising edge of Gate indicates the end of the second period. Sample Clock did not |
| assert during this period, so the counter discards the measurement of the second period. |
|
|
t5 | The rising edge of Gate indicates the end of the third period. Sample Clock asserts |
| during this period, so the USB M Series device stores the measurement in the buffer. |
|
|
Cascading Counters
You can internally route the Counter n Internal Output and Counter n TC signals of each counter to Gate inputs of the other counter. By cascading two counters together, you can effectively create a
Counter Filters
You can enable a programmable debouncing filter on each PFI signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency.
Note
The following is an example of low to high transitions of the input signal.
High to low transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the filter clock has sampled the signal high on N consecutive edges, the low to high transition is propagated to the rest of the circuit. The value of N depends on the filter setting; refer to Table
© National Instruments Corporation |