Chapter 2 Configuration and Installation
SCXI-1121 User Manual 2-44 www.natinst.com
Figure 2-17 shows the timing requirements on the SERCLK and
SERDATIN signals. You must observe these timing requirements for all
communications. Tdelay is a specification of the SCXI-1121.
Figure 2-17. Serial Data Timing Diagram
After the Slot-Select line to an SCXI-1121 has been asserted, you can write
to its Configuration Register and read from its Module ID Register by
following the protocols given below. The contents of the Module ID
Register are reinitialized by deasserting Slot-Select. After the 32 bits of
data are read from the Module ID Register, further data will be zeros until
reinitialization occurs.
To write to the Configuration Register, follow these steps:
1. Initial conditions:
SS* asserted low
SERDATIN = don't care
DAQD*/A = 0 (indicates data will be written to Configuration
Register)
SLOT0SEL* = 1
SERCLK = 1 (and has not transitioned since SS* went low)
2. For each bit to be written:
Establish the desired SERDATIN level corresponding to this bit.
SERCLK = 0
SERCLK = 1. Clock the data.
T
low
T
high
SERCLK
SERDATIN
SERDATOUT
T
setup
T
hold
T
delay
Tlow Minimum low time 65 nsec minimum
Thigh Minimum high time 400 nsec minimum
Tsetup SERDATIN setup time 200 nsec minimum
Thold SERDATIN hold time 200 nsec minimum
Tdelay SERDATOUT delay 350 nsec maximum