National Products DS90C3202 manual

DS90C32023.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color

receiver is designed to be used in Liquid Crystal Display

TVs, LCD Monitors, Digital TVs, and Plasma Display Panel

TVs. The DS90C3202 is designed to interface between the

digital video processor and the display device using the

low-power, low-EMI LVDS(Low Voltage Differential Signal-

ing) interface. The DS90C3202 converts up to ten LVDS

data streams back into 70 bits of parallel LVCMOS/LVTTL

data. The receiver can be programmed with rising edge or

falling edge clock. Optional wo-wire serial programming al-

lows fine tuning in development and production environ-

ments.With an input clock at 135 MHz, the maximum trans-

mission rate of each LVDS line is 945 Mbps, for an

aggregatethroughput rate of 9.45 Gbps (945 Mbytes/s). This

allows the dual 10-bit LVDSReceiver to support resolutions

up to HDTV.

nUp to 9.45 Gbit/s data throughput

n8 MHz to 135 MHz input clock support

nSupports up to QXGApanel resolutions

nSupports HDTV panel resolutions and frame rates up to

1920 x 1080p

nLVDS30-bit, 24-bit or 18-bit color data inputs

nSupports single pixel and dual pixel interfaces

nSupports spread spectrum clocking

nTwo-wireserial communication interface

nProgrammable clock edge and control strobe select

nPower down mode

n+3.3V supply voltage

n128-pin TQFP Package

nCompliant to TIA/EIA-644-A-2001 LVDSStandard

20147101

FIGURE 1. Receiver Block Diagram

September 2006