DS90C3202 Two-Wire Serial Interface Register Table (Continued)
Address | R/W | RESET | Bit # | Description | Default Value |
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30d/1eh | R/W | None | [7:5] | Reserved | 0000_0000 |
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| [4] | I/O disable control for RXE channel A, |
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| 1: disable, 0: enable (default) |
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| [3] | I/O disable control for RXE channel B, |
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| 1: disable, 0: enable (default) |
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| [2] | I/O disable control for RXE channel C, |
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| 1: disable, 0: enable (default) |
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| [1] | I/O disable control for RXE channel D, |
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| 1: disable, 0: enable (default) |
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| [0] | I/O disable control for RXE channel E, |
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| 1: disable, 0: enable (default) |
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31d/1fh | R/W | None | [7:6] | 11; LVTTL Outputs available as long as "NO CLK" is at | 0000_0000 |
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| HIGH regardless PLL lock or not |
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| 10; LVTTL Outputs available after 1K of CLK cycles |
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| detected & PLL generated strobes are within 0.5UI |
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| respect to REFCLK |
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| 01; LVTLL Outputs available after 2K of CLK cycles |
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| detected |
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| 00: default ; LVTTL Outputs available after 1K of CLK |
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| cycles detected |
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| [5] | 0: default; to select the size of wait counter between 1K |
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| or 2K, default is 1K |
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| [4] | I/O disable control for RXO channel A, |
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| 1: disable, 0: enable (default) |
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| [3] | I/O disable control for RXO channel B, |
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| 1 disable, 0: enable (default) |
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| [2] | I/O disable control for RXO channel C, |
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| 1: disable, 0: enable (default) |
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| [1] | I/O disable control for RXO channel D, |
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| 1: disable, 0: enable (default) |
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| [0] | I/O disable control for RXO channel E, |
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| 1: disable, 0: enable (default) |
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Note 13: Registers with RESET designated with “None” requires device to be power cycled to reset register values to their default state.
DS90C3202
21 | www.national.com |
