Worst Case Test Pattern | National Products DS90C3202 specification

AC Timing Diagrams (Continued)

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FIGURE 2. “Worst Case” Test Pattern

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FIGURE 3. Incremental Test Pattern

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FIGURE 4. Typical and Max ICC with Worse Case and Incremental Pattern

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FIGURE 5. LVCMOS/LVTTL Output Load and Transition Times

DS90C3202

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National Products DS90C3202 manual Worst Case Test Pattern

Contents

Block Diagram FeaturesGeneral Description Functional Description Typical Application Diagram Recommended Operating Conditions Electrical CharacteristicsLvds Receiver DC Specifications Absolute Maximum Ratings Note Receiver Supply Current Symbol Parameter Conditions Min Typ Max Units Symbol Parameter Condition Min Typ Max Units Reference Receiver Switching Characteristics AC Timing Diagrams Two-Wire Serial Communication Interface Worst Case Test Pattern Receiver Phase Lock Loop Wake-up Time Receiver Input Tolerance and Sampling Window RFB Lvttl Level Programmable Strobe Select RegisterAddress 29d/1dh bit 21 = 00b Receiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled 20147115 Lvds Input Mapping Receiver Ritol Min and Max DS90C3202 Receiver Pin Diagram Pin No Pin Name Pin Type Description DS90C3202 Pin Descriptions DS90C3202 Pin Descriptions RXOA4 Lvttl O/P Communicating with the DS90C3202 Control Registers Two-Wire Serial Communication Interface Description Address DS90C3202 Two-Wire Serial Interface Register TableReset Bit # Description Default Value Bit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver