National Products DS90C3202 - page 10

AC Timing Diagrams (Continued)

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RegisterAddress 29d/1dh bit [2:1] = 00b

FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled

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FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold TimeAdjustment — PTO Disabled

DS90C3202

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Contents

Main DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver General Description Features Block Diagram DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver Typical Application Diagram Functional Description DS90C3202 Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics DS90C3202 Electrical Characteristics Receiver Switching Characteristics Two-Wire Serial Communication Interface AC Timing Diagrams Page Page DS90C3202 Page Page Page Page Page DS90C3202 Pin Descriptions Page DS90C3202 Pin Descriptions Two-Wire Serial Communication Interface Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 Page Physical Dimensions DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver 128-Pin TQFP Package Order Number DS90C3202VS NS Package Number VJX128A