Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol | Parameter | Condition/ | Min | Typ | Max | Units |
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CLHT | LVCMOS/LVTTL | Rx clock out |
| 1.45 | 2.10 | ns |
| Time, CL = 8pF, (Figure 5) (Note 8) |
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| Register addr 28d/1ch, |
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| bit [2] (RCLK)=0b (Default), | Rx data out |
| 2.40 | 3.50 | ns |
| bit [1] (RXE) =0b (Default), |
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| bit [0] (RXO) =0b (Default) |
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CHLT | LVCMOS/LVTTL | Rx clock out |
| 1.35 | 2.20 | ns |
| Time, CL = 8pF, (Figure 5) (Note 8) |
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| Register addr 28d/1ch, |
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| bit [2] (RCLK)=0b (Default), |
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| Rx data out |
| 2.40 | 3.60 | ns | |
| bit [1] (RXE) =0b (Default), |
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| bit [0] (RXO) =0b (Default) |
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CLHT | LVCMOS/LVTTL | Rx clock out |
| 2.45 |
| ns |
Programmable | Time, CL = 8pF, (Figure 5) (Note 8) |
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adjustment | Register addr 28d/1ch, |
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| bit [2] (RCLK)=1b (Default), | Rx data out |
| 3.40 |
| ns |
| bit [1] (RXE) =1b (Default), |
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| bit [0] (RXO) =1b (Default) |
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CHLT | LVCMOS/LVTTL | Rx clock out |
| 2.35 |
| ns |
Programmable | Time, CL = 8pF, (Figure 5) (Note 8) |
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adjustment | Register addr 28d/1ch, |
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| bit [2] (RCLK)=0b (Default), |
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| Rx data out |
| 3.40 |
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| bit [1] (RXE) =0b (Default), |
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| bit [0] (RXO) =0b (Default) |
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RCOP | RCLK OUT Period (Figures 11, 12) (Note 8) | 7.4 | T | 125 | ns | |
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RCOH | RCLK OUT High Time (Figures 11, 12) | Rx clock out | 0.4T | 0.5T | 0.6T | ns |
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RCOL | RCLK OUT Low Time (Figures 11, 12) | Rx clock out | 0.4T | 0.5T | 0.6T | ns |
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RSRC | RxOUT Setup to RCLK OUT (Figures 11, 12) (Notes 8, 9) | 2.60 | 0.5T |
| ns | |
| Register addr 29d/1dh [2:1]= 00b (Default) |
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RHRC | RxOUT Hold to RCLK OUT (Figures 11, 12) (Notes 8, 9) | 3.60 | 0.5T |
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| Register addr 29d/1dh [2:1]= 00b (Default) |
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RSRC/RHRC | Register addr 29d/1dh [2:1] = 01b, (Figures 13, 14) |
| +1UI / |
| ns | |
Programmable | (Notes 2, 10) |
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Adjustment | RSRC increased from default by 1UI |
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| RHRC decreased from default by 1UI |
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| Register addr 29d/1dh [2:1] = 10b, (Figures 13, 14) |
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| (Notes 2, 10) |
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| +1UI |
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| RSRC decreased from default by 1UI |
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| RHRC increased from default by 1UI |
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| Register addr 29d/1dh [2:1] = 11b, (Figures 13, 14) |
| +2UI / |
| ns | |
| (Notes 2, 10) |
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| RSRC increased from default by 2UI |
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| RHRC decreased from default by 2UI |
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RPLLS | Receiver Phase Lock Loop Set (Figure 6) |
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| 10 | ms |
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RPDD | Receiver Powerdown Delay (Figure 7) |
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| 100 | ns |
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RPDL | Receiver Propagation Delay — Latency (Figure 8) |
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| 4*RCLK | ns | |
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RITOL | Receiver Input Tolerance | VCM = 1.25V, |
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| 0.25 | UI |
| (Figures 10, 16) (Notes 8, 10) | VID = 350mV |
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Note 8: Specification is guaranteed by characterization.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
DS90C3202
5 | www.national.com |
