Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 11 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
8. Functional description
This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an
analogsource, into digital data used by a LCD driver (pixel clock up to 200 MHz when
using 2 ICs).

8.1 IC analog video inputs

The video inputs are internally DC polarized. These inputs are AC coupled externally.

8.2 Clamps

Three independent parallel clamping circuits are used to clamp the video input
signals on the black level and to control the brightness level. The clamping code is
programmable between code−63.5 and +64 and from +120 to +136 in steps of
1⁄2LSB. The programming of the clamp value is achieved via an 8-bit DAC. Each
clamp must be able to correct an offset from±0.1 V to ±10 mV within 300 ns, and
correct the total offset in 10 lines.
The clamps are controlled by an external TTL positive going pulse (pinCLP). The
drop of the video signal is <1 LSB.
Normally,the circuit operates with a 0 code clamp, corresponding to the 0 ADC code.
This clamp code can be changed from −63.5 to +64 as represented in Figure 5, in
stepsof 1⁄2LSB. The digitized video signal is always between code 0 and code 255 of
the ADC. It is also possible to clamp from code120 to code 136 corresponding to
120 ADC code to 136 ADC code. Then clamping on code 128 of the ADC is possible.

8.3 Variable gain amplifiers

Three independent variable gain amplifiers are used to provide, to each channel, a
full-scale input range signal to the 8-bit ADC.The gain adjustment range is designed
so that for an input range varying from 0.4to 1.2 V (p-p), the output signal
corresponds to the ADC full-scale input of 1 V (p-p).
Toensure that the gain does not vary over the whole operating temperature range, an
external supplied reference voltage Vref= 2.5 V (DC), with a maximum variation of
100 ppm/°C, is used to calibrate the gain at the beginning of each video line before
the clamp pulse.
Fig 5. Clamp definition.
digitized
video
signal
video signal
CLP
clamp
programming
code 64
code 0
255
= 120 to 136
code −63.5
FCE471