Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 29 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
[1] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency).
Conversion-to-noise ratio: S/N= EB×6.02 + 1.76 dB.
[2] Output data acquisition is available after the maximum delay timetd(o), which is the time during which the data is available. All the
timings are given for a 10pF capacitive load. A higher load can be used but the timing must then be rechecked.
[3] The input current must be limited in accordance with the limiting values.
[4] The I2C-bus timings are given for a frequency of 100kbit/s (100 kHz). This bus can be used at a frequency of 400kbit/s (400 kHz).
Fig 11. Data timing diagram.td(s)
sample N + 1 sample N + 2
sample N
CKADCO n
FCE475
50 % = 1.4 V
1.4 V
2.4 V
0.4 V
Vin
DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR
td(o)
th(o)
tCPH tCPL
In − 1 In + 1 In + 2
In
fOE= 100 kHz; switchS1 connected to VCCD for tdLZ and tdZL; switchS1 connected to GND for tdHZ and tdZH.
Fig 12. Timing diagram and test conditions of 3-state output delay time.handbook, full pagewidth
output
data
output
data
OE 50%
50%
50%
10%
90%
LOW
TDA8752B
LOW
HIGH
HIGH
tdZH
tdZL
tdHZ
VCCD
tdLZ
3.3 kΩ
FCE476
S1
OE
VCCD
10 pF