NXP Semiconductors TDA8752B 8.4 ADCs, 8.5 ADC outputs, 8.6 Phase-locked loop

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 13 of 38

8.4 ADCs

The ADCs are 8-bit with a maximum clock frequency of 110Msps. The ADCs input

range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and

BOR). It will be at logic 1 when the signal is out of range of the full-scale of the ADCs.

Pipeline delay in the ADCs is 1clock cycle from sampling to data output.

The ADCs reference ladders regulators are integrated.

8.5 ADC outputs

ADC outputs are straight binary. An output enable pin (OE;active LOW) enables the

output status between active and high-impedance (OE= HIGH) to be switched; itis

recommended to load the outputs with a 10 pF capacitive load. The timing must be

checked very carefully if the capacitive load is more than 10pF.

8.6 Phase-locked loop

The ADCs are clockedeither by an internal PLL locked to the CKREF clock (all of the

PLL is on-chip except the loop ﬁlter capacitance) or by an external clock applied to

pin CKEXT. Selection is performed via the serial interface bus.

The reference clock (CKREF) range is between 15and 280 kHz. Consequently, the

VCO minimum frequency is 12 MHz and the maximum frequency is 110 MHz. The

gain of the VCO part can be controlled via the serial interface, depending on the

frequency range to which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump current, controlled by the

serial interface,must also be increased. The relationship between the frequency and

the current is given by the following equation:

(1)

Fig 7. Fine gain correction for a coarse gain GNCOARSE.

FCE473

128

160

227

255 G(max)

GNCOARSE

NCOARSE

G(min)

ADC

output code

coarse

value

(67 codes)

NFINE = 31

NFINE = 0 Vref

fn1

2π

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CZCP

+()DR⋅

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