NXP Semiconductors TDA8752B 9.2 I2C-bus protocol

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 22 of 38

9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.

9.2 I2C-bus protocol

The I2C-bus address of the circuit is 1001 1xx0.

Bits ‘A2’ and ‘A1’ are ﬁxed by the potential on pins ADD1 and ADD2. Thus, four

TDA8752Bs can be used on the same system, using the addresses for

ADD1 and ADD2 with the I2C-bus. Bit ‘A0’ must alwaysbe equal to logic 0 because it

is not possibleto read the data in the register. The timing and protocol for the I2C-bus

are standard. Two sequences are available, seeTab le 13 and 14.

Table 12: I2C-bus address

A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 1 ADD2 ADD1 0

Table 13: Address sequence for mode 0

Where: S = START condition, ACK= acknowledge and P = STOP condition.

S IC ADDRESS ACK SUBADDRESS

REGISTER1 ACK DATA

REGISTER1

(seeTa ble 4 )

ACK SUBADDRESS

REGISTER2 ACK ... P

Table 14: Address sequence for mode 1

Where: S = START condition, ACK= acknowledge and P = STOP condition.

S IC ADDRESS ACK SUBADDRESS

XXX1 1111 ACK D ATA

REGISTER1

(seeTa ble 4 )

ACK D ATA

REGISTER2 ACK ... P

Contents

Main TDA8752B Triple high-speed Analog-to-Digital Converter 110 Msps Rev. 03 21 July 2000 Product specication 1. General description 2. Features 3. Applications 4. Quick reference data 5. Ordering information 6. Block diagram RED CHANNEL BLUE CHANNEL TDA8752B Fig 1. Block diagram. Philips Semiconductors TDA8752B Fig 2. Red channel diagram. Fig 3. PLL diagram. 7. Pinning information TDA8752BH Fig 4. Pin conguration. 7.1 Pinning Philips Semiconductors TDA8752B 7.2 Pin description Page Triple high-speed Analog-to-Digital Converter 110 Msps 8. Functional description 8.1 IC analog video inputs 8.2 Clamps 8.3 Variable gain ampliers Page 8.4 ADCs 8.5 ADC outputs 8.6 Phase-locked loop Page 8.7 I2C-bus and 3-wire serial bus interface Slave at 180 deg phase shift with respect to pinCKADCO of the master TDA8752B. Fig 9. Dual TDA8752B solution for pixel clock rate with a single phase adjustment (100to 200 MHz). PLL Master TDA8752B (even pixels) PLL Slave TDA8752B (odd pixels) 9. I2C-bus and 3-wire serial bus interfaces 9.1 Register denitions 9.2 I2C-bus protocol 9.3 3-wire serial bus protocol 10. Limiting values 11. Thermal characteristics 12. Characteristics Page Page Page Page Fig 11. Data timing diagram. Fig 12. Timing diagram and test conditions of 3-state output delay time. V =25 =5V; T C. 13. Application information TDA8752B Fig 13. Application diagram. 14. Package outline Fig 14. SOT317-2 package outline. QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 15. Handling information 16. Soldering 16.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 16.2 Reow soldering 17. Revision history 18. Data sheet status 19. Denitions 21. Licenses 20. Disclaimers Philips Semiconductors - a worldwide company Internet: http://www.semiconductors.philips.com Contents