NXP Semiconductors TDA8752B ,

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 15 of 38

The PLL can be used in three different methods:

•The IC can be used as stand-alone with a sampling frequency of up to 110 MHz.

•When an RGB signal is at a pixel frequency exceeding 100to 200 MHz, it is

possible to follow one of the two possibilities given below:

–Using one TDA8752B: the sampling rate can be reduced by a factor of two, by

sampling the evenpixels in the even frame and the odd pixels in the odd frame.

Pin INV is used to toggle between the frames.

–Using two TDA8752Bs: the PLL of the master TDA8752B is used to drive both

ADC clocks.The PLL of the slave TDA8752B is disconnected and the CKBO of

themaster TDA8752B is connected to pin CKEXT of the TDA8752B master and

CKAO to the slave TDA8752B. In this case, on pinCKAO CKBO will be the

output (with bit CKAB of the master at logic 1).

The master TDA8752B is used to sample the even pixels and the slave

TDA8752Bfor odd pixels, using a 180 deg phase shift between the clocks (both

pins CKADCO). The master chip and the slave chip have their pinINV LOW,

which guarantees the 180 deg shift ADC clock drive. Itis then necessar y to

adjust phase B of the master chip.Special care should be taken with the quality

of the input signal (input settling time).

If CKREFO output signal at the master chip is needed, it is possible to use one

of the two phase A values in order to avoid set-up and hold problems in the

SYNCHRO function; e.g. PHASEA= 100 000 and PHASEA = 111111.

•When INV is LOW, CKADCO is equal to CKEXT inverted.

tCKAO=t

CLK(buffer)+t

phaseselector [tCLK(buffer) = 10 ns and tphaseselector =].

tCKREFO= either tCKAO −if PHASEA ≥01000 or tCKAO + if PHASEA< 01000.

Fig 8. Timing diagram.

tCKAO

tCKREFO

FCE470

CKAO

CKREFO

CKREF

tphase selector

2π

---------------------------TCLK(pixel)

TCLK(pixel)

------------------------ TCLK(pixel)

------------------------