¡ Semiconductor |
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| MSM80C154S/83C154S | ||||
Interrupt enable register (IE) |
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NAME | ADDRESS | MSB |
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| LSB |
7 | 6 | 5 |
| 4 |
| 3 |
| 2 | 1 | 0 | ||
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IE | 0A8H | EA | — | ET2 |
| ES |
| ET1 |
| EX1 | ET0 | EX0 |
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BIT LOCATION | FLAG |
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| FUNCTION |
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IE.0 | EX0 | Interrupt control bit for external interrupt 0. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.1 | ET0 | Interrupt control bit for timer interrupt 0. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.2 | EX1 | Interrupt control bit for external interrupt 1. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.3 | ET1 | Interrupt control bit for timer interrupt 1. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.4 | ES | Interrupt control bit for serial port. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.5 | ET2 | Interrupt control bit for timer interrupt 2. |
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| Interrupt disabled when bit is "0". |
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| Interrupt enabled when bit is "1". |
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IE.6 | — | Reserved bit. The output data is "1" if the bit is read. |
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IE.7 | EA | Overall interrupt control bit. |
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| All interrupts are disabled when bit is "0". |
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| All interrupts are controlled by IE.0 thru IE.5 when bit is "1". |
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