Omega Engineering OME-PIO-D96 manual D/I/O Architecture

2.4D/I/O Architecture

I/O select (Sec. 3.3.7)

RESET\ (Sec. 3.3.1)

disable\

Data

input Latch

(Sec. 3.3.8)

Clock input

D/O latch CKT

disable

Data

Buffer input

(Sec. 3.3.8)

Clock input

D/I buffer CKT

D/I/O

•The RESET\ is in Low-state Æ all D/I/O are disabled

•The RESET\ is in High-state Æ all D/I/O are enabled

•If D/I/O is configured as D/I port Æ D/I= external input signal

•If D/I/O is configured as D/O port Æ D/I = read back D/O

•If D/I/O is configured as D/I port Æ send to D/O will change the D/O latch register only. The D/I & external input signal will not change

OME-PIO-D96 User Manual (Ver.1.1, Mar/2003) ---- 8