2-5
2 Instructions
CP1E CPU Unit Instructions Reference Manual(W483)
Sequence Input Instructions
2
Sequence Input Instructions

Differentiated and Immediate Refreshing Instructions

•The LOAD, AND, and OR instructions have differentiated and immediate refreshing variations in addi-
tion to their ordinary forms, and there are also two combinations available.
•The LOAD NOT, AND NOT, OR NOT, OUT, and OUT NOT instructions have immediate refreshing
variations in addition to their ordinary forms.
•The I/O timing for data handled by instructions differs for ordinary and differentiated instructions,
immediate refreshing instructions, and immediate refreshing differentiated instructions.
•Ordinary and differentiated instructions are executed using data input by previous I/O refresh pro-
cessing, and the results are output with the next I/O processing. Here “I/O refreshing” means the data
exchanged between the CPU’s internal memory and the I/O Unit.
•In addition to the above I/O refreshing, an immediate refresh instruction exchanges data with the I/O
Unit for those words that are accessed by the instruction. An immediate refresh instruction refreshes
eight bits simultaneously (leftmost or rightmost eight bits) in addition to the specified bit.
Immediate refresh instructions (i.e., instructions with !) cannot be used for I/O on CP Expansion
Units or CP Expansion I/O Units. Use IORF(097) for I/O on CP Expansion Units or CP Expansion I/O
Units.
Instruction variation Mnemonic Function I/O refresh
Ordinary LD, AND, OR, LD NOT,
AND NOT, OR NOT
The ON/OFF status of the specified bit is
taken by the CPU with cyclic refreshing,
and it is reflected in the next instruction
execution.
Cyclic refreshing
OUT, OUT NOT After the instruction is executed, the
ON/OFF status of the specified bit is out-
put with the next cyclic refreshing.
Differentiated up @LD, @AND, @OR The instruction is executed once when
the specified bit turns from OFF to ON
and the ON state is held for one cycle.
Differentiated down %LD, %AND, %OR The instruction is executed once when
the specified bit turns from ON to OFF
and the ON state is held for one cycle.
Immediate refresh !LD, !AND, !OR, !LD NOT,
!AND NOT, !OR NOT
The input data for the specified bit is
taken by the CPU and the instruction is
executed.
Before instruction execu-
tion
!OUT, !OUT NOT After the instruction is executed, the data
for the specified bit is output.
After instruction execution
Differentiated up /
immediate refresh
!@LD, !@AND, !@OR The input data for the specified bit is
refreshed by the CPU, and the instruc-
tion is executed once when the bit turns
from OFF to ON and the ON state is held
for one cycle.
Before instruction execu-
tion
Differentiated down /
immediate refresh
!%LD, !%AND, !%OR The input data for the specified bit is
refreshed by the CPU, and the instruc-
tion is executed once when the bit turns
from ON to OFF and the ON state is held
for one cycle.