Summary of Special Function Registers, Cpum | Panasonic MN101C00

Chapter 10 Appendices

8-4 Summary of Special Function Registers

Address

Register

Bit Symbol

Reference �

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

page�

STOP

HALT

OSC1

OSC0

�

CPUM�

MN101C00 seriesﾞ

�

X’3F00’

�

Must be set�

STOP�

HALT�

Oscillation control

LSI Manual�

to "0"�

transfer requesttransfer request

�

MEMCTR�

IOW1

IOW0

IVBA

�

�

IRWE

�

X’3F01’

�

II/0 bus wait value set

Specifiesbaseaddress�

�

30

ofinterruptvectortable

WDCTR�

WDEN

�

X’3F02’

�

Watchdog � � 89

timer table

DLYCTR�

DLYS1

DLYS0

�

X’3F03’

�

Sets oscillation �

89

stabilization wait period

X’3F0E’

�

�

�

�

EXADV

P0OUT�

P0OUT6

P0OUT2

P0OUT1

P0OUT0

41，45

X’3F10’

�

Port 0 output

P1OUT�

P1OUT4

P1OUT3

P1OUT2

P1OUT1

P1OUT0

41，45

X’3F11’

�

Port 1 output

P2OUT�

P2OUT7

41，45

X’3F12’

�

Port 2 output

X’3F13’

�

�Disables to use

X’3F14’

�

�Disables to use

X’3F15’

�

�Disables to use

P6OUT�

P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0

41，45

X’3F16’

�

Port 6 output

P7OUT�

P7OUT0

41，45

X’3F17’

�

Port 7�

output

P8OUT�

P8OUT7

P8OUT6

P8OUT5

P8OUT4

P8OUT3

P8OUT2

P8OUT1

P8OUT0

41，45

X’3F18’

�

Port 8 output

X’3F1F’

Disables�to use

�

P0IN�

P0IN6

P0IN2

P0IN1

P0IN0

41，45

X’3F20’

�

Port 0 input

P1IN�

P1IN4

P1IN3

P1IN2

P1IN1

P1IN0

41，45

X’3F21’

�

Port 1 input

X’3F22’

�

P2IN�

P2IN2

P2IN1

P2IN0

41，45

Port 2input

X’3F23’

�Disables��to use

�

Summary of Special Function Registers 149

Image 163

Panasonic MN101C00 user manual Summary of Special Function Registers, Cpum

Contents

Pub. No -011E MN101C115/117 LSI User’s ManualPage Page Under plannin Unit Byte How to Read This Manual Summary Precautions and warningsSubtitle Sub-subtitle Main text Key information Finding Desired Information Page Page Contents0 Contents Port Functions Serial Functions Appendices Page Chapter Overview Model ROM Size RAM Size Classification Product OverviewOverview Product Summary Hardware Functions Operation modes Normal mode LED driver function 8 pins Ports Pin Diagram Pins MN101C117/115 MN101C117/115 Pin No Name Type Pin Function SummaryFunction Description Rmout 1 Pin Function Summary 2/4 TXD 1 Pin Function Summary 3/4 Mmod 1 Pin Function Summary 4/4 MN101C00 Block DiagramBit timer Conversion Overview of Functions Absolute Maximum Ratings ∗2 ∗3 Electrical CharacteristicsContents Model MN101C117/115 Parameter Symbol Rating Unit Crystal oscillator 1 Fig Operating ConditionsSupply voltage Operating speed ∗ External clock input 2 XI XO is unconnected*2 External clock input 1 OSC1 OSC2 is unconnected 9VDD 1VDD Twh1twl1 Twr1twf1 Supply current no load at output ∗ DC Characteristics Input pin 3-1 P21 Schmitt trigger input Input pin 3-2 P21 when used as SensInput pin 1 Mmod Input pin 2 P20, P22~P23 Schmitt trigger input Input pin 4 PA0~PA7 Sens pin Pin 8 P70 to P71 Pin 5 P27 RSTPin 6 P00 to P06, P10 to P14 Schmitt trigger input Pin 7 , P60 to P67 Pin 9 P80~P87 4 A/D Converter Characteristics ROM Option Option Model Name MN101C Date SE No Customer Option Form Package code SDIP042-P-0600 Unit mm Outline Drawings 2 44-QFP Package code QFP044-P-1010 Unit mm 3 48-QFH Package code QFH048-P-0707 Unit mm Basic CPU Functions Overview Memory ConfigurationAddress Space 03FFX Special Function Registers03FAX 03FBX 03FCX 03FDX 03FEX Memctr Bus InterfaceControl Registers Memory control registerMEMCTR Low Address High InterruptsAccepting and Returning from Interrupts New SP Operation when Returning from Interrupt Interrupt Sources and Vector Addresses Non-maskable Interrupt Control Register Nmicr Interrupt Control Registers XxxLV1 XxxLV0 XxxIE XxxIR At reset Releasing the Reset ResetRST pin Clock cycles 200ns for a 20MHz oscillation Chapter Port Functions Port 0 P0 1 Status When Port Is Reset single-chip mode2 Port 0 Functions 4 Port 2 Functions Port 1 P13 Port 1 Functions Port 2 P2 Port 8 Functions Port 7 P7Port 7 Functions Port 8 P8 Name Address Function Port Control Registers Port Control Registers 2/2 At reset 000 At resetAt reset XXX At reset Xxxxx P7IN1 P7IN0 P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 1 Port Control Registers 2/2 2 I/O Port Control Registers O port Special function pin Pin Control Registers Port Output/Input Mode Registers P00,P02,P10 to P14 I/O Port Configuration and Functions Control Address P01P01 Pull-up Control bit Resistor Register PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA0 to PA7 P20 P22 P23 Pull-up Control bit Pin Configuration for P20, P22 to P23Port input Control bit P21 5 Configuration and Functions of P21 P27 6 Configuration and Functions of P27 Direction Configuration and Functions of P70P70 to P71 P70 P71 P60 to P67,P80 to P87 8 Configuration and Functions of P60 to P67 Chapter Timer Functions Fosc,fx/2 PWM outputClock Fs/4 Source 1 Timers 2, 3 Block Diagram 2 Timer 4 Block Diagram 3 Timer 5/Time Base Block Diagram Dlyctr WdirqWdctr MUX Rmctr 5 Remote Control Transmission Block Diagram Bit 8-bit Timer Operation timers 2SIF0 1 Binary Counter 2 TM2BC Count Timing Operation 64 8-bit Timer Operation timers 2 Matches compare register Binary counter 3 Timer Pulse Output Timing 4 PWM Output Timing Clock PWM output 6 PWM Output Timing when TM2OC register is XFF Disable the timer 2 interrupt 16-bit Timer Operation timer 1 Binary Counter 4 TM4BC Count Timing Timer Functions Matches TM4OCH, TM4OCL register Binary counter 4 Pulse Added Type PWM Output Added pulse Setting the Added Pulse Position1 Pulse-Added PWM OutputFigure Repeated 256 times FFPosition Timer Functions Timer Operation 8-bit Timer Operation timer Time Base Operation Base Time Settings TM5IR2 toClock Source Setup and Operation Watchdog Timer Operation 1 Remote Control Carrier Output Waveform Remote Control Output Operation Buzzer Output Buzzer Output Setup and Operation Timer Control Registers Timer Function Control RegistersName Address Function TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 Programmable Timer/CountersTM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 Binary counter 4 TM4BCH upper 8 bits Compare register 4 TM4OCL lower 8 bitsBinary Counter 4 TM4BCL X03F64, R Binary Counter 4 TM4BCH X03F65, R Input Capture Register TM4ICL X03F66, R Input capture register TM4ICL lower 8 bitsTM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 TM2EN Timer Mode RegistersTM2MD TM2PWM TM3EN Timer 3 mode register TM3MDTM3MD TM3PWM TM4EN Timer 4 mode register TM4MDTM4MD IRQ0 IRQ1 IRQ2 TM4PWM TM5IR0 Timer 5 mode register TM5MDTM5MD TM5CK0 Watchdog timer control register Wdctr Timer Control Registers Rmoen Remote control carrier output control register Rmctr Chapter Serial Functions Serial Functions 1 Serial 0 Block Diagram Synchronous Serial Interface Serial Functions SBT SBO SBTSBO SC0BSY Serial Functions Start condition enabled Start condition disabled 1 Serial Data Input Edge and Output Edge serial interface Serial Interface Transfer TimingReceive Data Input Edge Transmit Data Output Edge SBI0 SBT0SBO0 Half-duplex Uart Serial Interface 1 Uart Transmission Timing Reception 2 Uart Reception Timing How to Use the Baud Rate Timer SC0RXB Serial Interface Control Registers SC0RXB Transmit/Receive Shift Registers, Receive Data BufferSerial interface 0 transmit/receive shift register SC0TRB SC0TRB SC0STE Serial Interface Mode RegistersSerial interface 0 mode register SC0MD0 SC0MD0 Serial interface 0 mode register 1 SC0MD1 SC0BRKE Serial interface 0 mode register 2 SC0MD2SC0MD2 SC0NPE Serial interface 0 mode register 3 SC0MD3 Serial interface 0 control register SC0CTR Serial Interface Control Register Chapter Conversion Functions AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANCTR0ANCTR1 ANBUF1 ANBUF0 1 A/D Conversion Timing A/D Conversion 2 Recommended Circuit When Using A/D Conversion 1 A/D Converter Control Registers A/D Converter Control Registers D control register 0 ANCTR0 2 A/D Control Register AnctrAN0 ANCTR1 Anst D conversion control register 1 ANCTR1 5 4 3 2 1 3 A/D Buffers Anbuf Chapter AC Zero-Cross Circuit/Noise Filter 1 P21 Input Circuit Block Diagram 1 AC Line Waveform and IRQ Generation Timing AC Zero-Cross Circuit Operation Noise Filter 1 Noise Filtering Circuit Block Diagram Sampling Input Waveform after noise filtering Example Input and Output Waveforms for Noise Filter Nfctr AC Zero-Cross Control Register Nfctr Noise Filter Control Register NfctrNF0EN 128 Appendices8 Eprom Versions Appendices Appendices There are no other functional differences Characteristics of Eprom VersionOperating temperature Tion start control,runaway Internal ROM final address data Fit in the writing adapter and position the No.1 pin Writing to Microcomputer with Internal Eprom Data I/O Vendor Appendices 2 Option bitAddress X07FFF Option Bit Package Code SDIP042-P-0600 Writing Adapter Connection 4 MN101CP117-BLBCEPROM Writing Adapter Connections Package code QFP044-P-1010 Pin pitch 8mm 5 MN101CP117-HP Eprom Writing Adapter connections Package code QFH048-P-0707 Pin pitch 5mm Instruction Set 1101 111a #16 ∗1 d4 sign extended ∗2 d7 sign extended ∗3 d11 sign extended 0010 0011 0001 D11 0011 0100 0bp Ver2.01997.9.26 MN101C00 Series Instruction MAP Instruction Map Cbeq #8,abs16,d7/11 Cbne #8,abs16,d7/11 Cpum Summary of Special Function Registers P6IN7 P2PLU2 TM2BC4 TM2BC3 TM2BC2 TM2BC1 Nmicr Wdir TBLV0 Tbir Matsushita Electronics Corporation MN101C115 Sales Offices