Watchdog Timer Operation, Setup and Operation | Panasonic MN101C00

Chapter 4 Timer Functions

4-6 Watchdog Timer Operation

4-6-1 Overview

The watchdog timer is controlled by the watchdog control register (WDCTR) and can

be used for runaway program detection.

The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to "0." Therefore, if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1, WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1/4TWD. If the WDEN bit is

to be repeatedly cleared and set at regular intervals, those operations should be performed within 1/4 of the TWD period.

4-6-2 Setup and Operation

(1)Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start the watchdog timer.

(2)Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed amount of time (TWD), and then resetting the WDEN flag to "1."

If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed amount of time passes.

(3)When an illegal operation is detected, the program encoded at the location of the WDT interrupt routine is executed.

TWD is set by the ROM option as fs/216, fs/218, or fs/220.

Illegal operation detection period vs. WDEN clear period is shown by the following formula:

Illegal operation detection period > [WDEN clear period] x 4

When software resetting is not triggered by WDT interrupt, hardware resetting (low level output at the reset terminal) takes place at the next WDT interrupt.

78 Watchdog Timer Operation

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Panasonic MN101C00 user manual Watchdog Timer Operation, Setup and Operation

Contents

MN101C115/117 LSI User’s Manual Pub. No -011EPage Page How to Read This Manual Under plannin Unit Byte Precautions and warnings Subtitle Sub-subtitleMain text Key information Summary Finding Desired Information Page Page Contents0 Contents Port Functions Serial Functions Appendices Page Chapter Overview Product Overview OverviewProduct Summary Model ROM Size RAM Size Classification Hardware Functions LED driver function 8 pins Ports Operation modes Normal mode Pins Pin Diagram MN101C117/115 MN101C117/115 Function Description Pin Function SummaryPin No Name Type 1 Pin Function Summary 2/4 Rmout 1 Pin Function Summary 3/4 TXD 1 Pin Function Summary 4/4 Mmod Block Diagram Bit timer ConversionOverview of Functions MN101C00 Electrical Characteristics Contents Model MN101C117/115Parameter Symbol Rating Unit Absolute Maximum Ratings ∗2 ∗3 Operating Conditions Supply voltageOperating speed ∗ Crystal oscillator 1 Fig External clock input 1 OSC1 OSC2 is unconnected External clock input 2 XI XO is unconnected*2 9VDD 1VDD Twh1twl1 Twr1twf1 DC Characteristics Supply current no load at output ∗ Input pin 3-2 P21 when used as Sens Input pin 1 MmodInput pin 2 P20, P22~P23 Schmitt trigger input Input pin 3-1 P21 Schmitt trigger input Sens pin Input pin 4 PA0~PA7 Pin 5 P27 RST Pin 6 P00 to P06, P10 to P14 Schmitt trigger inputPin 7 , P60 to P67 Pin 8 P70 to P71 4 A/D Converter Characteristics Pin 9 P80~P87 Option ROM Option Option Form Model Name MN101C Date SE No Customer Outline Drawings Package code SDIP042-P-0600 Unit mm Package code QFP044-P-1010 Unit mm 2 44-QFP Package code QFH048-P-0707 Unit mm 3 48-QFH Basic CPU Functions Address Space Memory ConfigurationOverview Special Function Registers 03FAX 03FBX 03FCX03FDX 03FEX 03FFX Bus Interface Control RegistersMemory control registerMEMCTR Memctr Interrupts Accepting and Returning from InterruptsNew SP Low Address High Operation when Returning from Interrupt Interrupt Sources and Vector Addresses Interrupt Control Registers Non-maskable Interrupt Control Register Nmicr XxxLV1 XxxLV0 XxxIE XxxIR At reset RST pin Clock cycles 200ns for a 20MHz oscillation ResetReleasing the Reset Chapter Port Functions 2 Port 0 Functions 1 Status When Port Is Reset single-chip modePort 0 P0 Port 1 P1 3 Port 1 FunctionsPort 2 P2 4 Port 2 Functions Port 7 P7 Port 7 FunctionsPort 8 P8 Port 8 Functions Port Control Registers Name Address Function Port Control Registers 2/2 At reset At reset XXXAt reset Xxxxx At reset 000 1 Port Control Registers 2/2 P7IN1 P7IN0 P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 2 I/O Port Control Registers Port Output/Input Mode Registers O port Special function pin Pin Control Registers I/O Port Configuration and Functions P00,P02,P10 to P14 P01 P01 Pull-up Control bitResistor Register Control Address PA0 to PA7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port input Control bit Pin Configuration for P20, P22 to P23P20 P22 P23 Pull-up Control bit 5 Configuration and Functions of P21 P21 6 Configuration and Functions of P27 P27 Configuration and Functions of P70 P70 to P71P70 P71 Direction 8 Configuration and Functions of P60 to P67 P60 to P67,P80 to P87 Chapter Timer Functions PWM output ClockFs/4 Source Fosc,fx/2 1 Timers 2, 3 Block Diagram 2 Timer 4 Block Diagram 3 Timer 5/Time Base Block Diagram Wdirq WdctrMUX Dlyctr 5 Remote Control Transmission Block Diagram Rmctr SIF0 8-bit Timer Operation timers 2Bit Operation 1 Binary Counter 2 TM2BC Count Timing 64 8-bit Timer Operation timers 2 3 Timer Pulse Output Timing Matches compare register Binary counter 4 PWM Output Timing 6 PWM Output Timing when TM2OC register is XFF Clock PWM output Disable the timer 2 interrupt 16-bit Timer Operation timer 1 Binary Counter 4 TM4BC Count Timing Timer Functions Matches TM4OCH, TM4OCL register Binary counter 4 Pulse Added Type PWM Output Setting the Added Pulse Position 1 Pulse-Added PWM OutputFigureRepeated 256 times FFPosition Added pulse Timer Functions 8-bit Timer Operation timer Timer Operation Clock Source Base Time Settings TM5IR2 toTime Base Operation Watchdog Timer Operation Setup and Operation Remote Control Output Operation 1 Remote Control Carrier Output Waveform Buzzer Output Setup and Operation Buzzer Output Name Address Function Timer Function Control RegistersTimer Control Registers TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 Programmable Timer/CountersTM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 Compare register 4 TM4OCL lower 8 bits Binary Counter 4 TM4BCL X03F64, RBinary Counter 4 TM4BCH X03F65, R Binary counter 4 TM4BCH upper 8 bits TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 Input capture register TM4ICL lower 8 bitsInput Capture Register TM4ICL X03F66, R Timer Mode Registers TM2MDTM2PWM TM2EN Timer 3 mode register TM3MD TM3MDTM3PWM TM3EN Timer 4 mode register TM4MD TM4MDIRQ0 IRQ1 IRQ2 TM4PWM TM4EN Timer 5 mode register TM5MD TM5MDTM5CK0 TM5IR0 Timer Control Registers Watchdog timer control register Wdctr Remote control carrier output control register Rmctr Rmoen Chapter Serial Functions Serial Functions 1 Serial 0 Block Diagram Synchronous Serial Interface Serial Functions SBT SBOSC0BSY SBT SBO Serial Functions Start condition enabled Start condition disabled Receive Data Input Edge Transmit Data Output Edge Serial Interface Transfer Timing1 Serial Data Input Edge and Output Edge serial interface SBO0 SBT0SBI0 Half-duplex Uart Serial Interface 1 Uart Transmission Timing Reception 2 Uart Reception Timing How to Use the Baud Rate Timer Serial Interface Control Registers SC0RXB Transmit/Receive Shift Registers, Receive Data Buffer Serial interface 0 transmit/receive shift register SC0TRBSC0TRB SC0RXB Serial Interface Mode Registers Serial interface 0 mode register SC0MD0SC0MD0 SC0STE Serial interface 0 mode register 1 SC0MD1 Serial interface 0 mode register 2 SC0MD2 SC0MD2SC0NPE SC0BRKE Serial interface 0 mode register 3 SC0MD3 Serial Interface Control Register Serial interface 0 control register SC0CTR Chapter Conversion Functions ANCTR1 ANBUF1 ANBUF0 ANCTR0AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Conversion 1 A/D Conversion Timing 2 Recommended Circuit When Using A/D Conversion A/D Converter Control Registers 1 A/D Converter Control Registers AN0 2 A/D Control Register AnctrD control register 0 ANCTR0 D conversion control register 1 ANCTR1 ANCTR1 Anst 3 A/D Buffers Anbuf 5 4 3 2 1 Chapter AC Zero-Cross Circuit/Noise Filter 1 P21 Input Circuit Block Diagram AC Zero-Cross Circuit Operation 1 AC Line Waveform and IRQ Generation Timing 1 Noise Filtering Circuit Block Diagram Noise Filter Example Input and Output Waveforms for Noise Filter Sampling Input Waveform after noise filtering AC Zero-Cross Control Register Nfctr NF0EN Noise Filter Control Register NfctrNfctr 128 Appendices8 Eprom Versions Appendices Appendices Characteristics of Eprom Version Operating temperatureTion start control,runaway Internal ROM final address data There are no other functional differences Writing to Microcomputer with Internal Eprom Fit in the writing adapter and position the No.1 pin Vendor Data I/O Appendices Option Bit 2 Option bitAddress X07FFF Writing Adapter Connection Package Code SDIP042-P-0600 Package code QFP044-P-1010 Pin pitch 8mm 4 MN101CP117-BLBCEPROM Writing Adapter Connections Package code QFH048-P-0707 Pin pitch 5mm 5 MN101CP117-HP Eprom Writing Adapter connections Instruction Set 1101 111a #16 ∗1 d4 sign extended ∗2 d7 sign extended ∗3 d11 sign extended 0010 0011 0001 D11 0011 0100 0bp Ver2.01997.9.26 Instruction Map MN101C00 Series Instruction MAP Cbeq #8,abs16,d7/11 Cbne #8,abs16,d7/11 Summary of Special Function Registers Cpum P6IN7 P2PLU2 TM2BC4 TM2BC3 TM2BC2 TM2BC1 Nmicr Wdir TBLV0 Tbir MN101C115 Matsushita Electronics Corporation Sales Offices