Operation when Returning from Interrupt | Panasonic MN101C00

Chapter 2 Basic CPU Functions

■Operation when Returning from Interrupt

After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received.

The processing sequence for the return from interrupt instruction, RTI, is listed below.

1.The processor status word (PSW) is pulled from the stack. (SP)

2.The program counter(PC = return address) is pulled from the stack. (SP+1 to 3)

3.The handy address register (HA) is pulled from the stack. (SP+4, 5)

4.The SP is pulled. (SP+6 → SP)

5.Execution branches to the address indicated by the PC.

32 Interrupts

Image 46

Panasonic MN101C00 user manual Operation when Returning from Interrupt

Contents

MN101C115/117 LSI User’s Manual Pub. No -011EPage Page How to Read This Manual Under plannin Unit Byte Main text Key information Precautions and warningsSubtitle Sub-subtitle Summary Finding Desired Information Page Page Contents0 Contents Port Functions Serial Functions Appendices Page Chapter Overview Product Summary Product OverviewOverview Model ROM Size RAM Size Classification Hardware Functions LED driver function 8 pins Ports Operation modes Normal mode Pins Pin Diagram MN101C117/115 MN101C117/115 Pin No Name Type Pin Function SummaryFunction Description 1 Pin Function Summary 2/4 Rmout 1 Pin Function Summary 3/4 TXD 1 Pin Function Summary 4/4 Mmod Overview of Functions Block DiagramBit timer Conversion MN101C00 Parameter Symbol Rating Unit Electrical CharacteristicsContents Model MN101C117/115 Absolute Maximum Ratings ∗2 ∗3 Operating speed ∗ Operating ConditionsSupply voltage Crystal oscillator 1 Fig External clock input 1 OSC1 OSC2 is unconnected External clock input 2 XI XO is unconnected*2 9VDD 1VDD Twh1twl1 Twr1twf1 DC Characteristics Supply current no load at output ∗ Input pin 2 P20, P22~P23 Schmitt trigger input Input pin 3-2 P21 when used as SensInput pin 1 Mmod Input pin 3-1 P21 Schmitt trigger input Sens pin Input pin 4 PA0~PA7 Pin 7 , P60 to P67 Pin 5 P27 RSTPin 6 P00 to P06, P10 to P14 Schmitt trigger input Pin 8 P70 to P71 4 A/D Converter Characteristics Pin 9 P80~P87 Option ROM Option Option Form Model Name MN101C Date SE No Customer Outline Drawings Package code SDIP042-P-0600 Unit mm Package code QFP044-P-1010 Unit mm 2 44-QFP Package code QFH048-P-0707 Unit mm 3 48-QFH Basic CPU Functions Overview Memory ConfigurationAddress Space 03FDX 03FEX Special Function Registers03FAX 03FBX 03FCX 03FFX Memory control registerMEMCTR Bus InterfaceControl Registers Memctr New SP InterruptsAccepting and Returning from Interrupts Low Address High Operation when Returning from Interrupt Interrupt Sources and Vector Addresses Interrupt Control Registers Non-maskable Interrupt Control Register Nmicr XxxLV1 XxxLV0 XxxIE XxxIR At reset Releasing the Reset ResetRST pin Clock cycles 200ns for a 20MHz oscillation Chapter Port Functions Port 0 P0 1 Status When Port Is Reset single-chip mode2 Port 0 Functions Port 2 P2 Port 1 P13 Port 1 Functions 4 Port 2 Functions Port 8 P8 Port 7 P7Port 7 Functions Port 8 Functions Port Control Registers Name Address Function Port Control Registers 2/2 At reset Xxxxx At resetAt reset XXX At reset 000 1 Port Control Registers 2/2 P7IN1 P7IN0 P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 2 I/O Port Control Registers Port Output/Input Mode Registers O port Special function pin Pin Control Registers I/O Port Configuration and Functions P00,P02,P10 to P14 Resistor Register P01P01 Pull-up Control bit Control Address PA0 to PA7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 P20 P22 P23 Pull-up Control bit Pin Configuration for P20, P22 to P23Port input Control bit 5 Configuration and Functions of P21 P21 6 Configuration and Functions of P27 P27 P70 P71 Configuration and Functions of P70P70 to P71 Direction 8 Configuration and Functions of P60 to P67 P60 to P67,P80 to P87 Chapter Timer Functions Fs/4 Source PWM outputClock Fosc,fx/2 1 Timers 2, 3 Block Diagram 2 Timer 4 Block Diagram 3 Timer 5/Time Base Block Diagram MUX WdirqWdctr Dlyctr 5 Remote Control Transmission Block Diagram Rmctr Bit 8-bit Timer Operation timers 2SIF0 Operation 1 Binary Counter 2 TM2BC Count Timing 64 8-bit Timer Operation timers 2 3 Timer Pulse Output Timing Matches compare register Binary counter 4 PWM Output Timing 6 PWM Output Timing when TM2OC register is XFF Clock PWM output Disable the timer 2 interrupt 16-bit Timer Operation timer 1 Binary Counter 4 TM4BC Count Timing Timer Functions Matches TM4OCH, TM4OCL register Binary counter 4 Pulse Added Type PWM Output Repeated 256 times FFPosition Setting the Added Pulse Position1 Pulse-Added PWM OutputFigure Added pulse Timer Functions 8-bit Timer Operation timer Timer Operation Time Base Operation Base Time Settings TM5IR2 toClock Source Watchdog Timer Operation Setup and Operation Remote Control Output Operation 1 Remote Control Carrier Output Waveform Buzzer Output Setup and Operation Buzzer Output Timer Control Registers Timer Function Control RegistersName Address Function TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 Programmable Timer/CountersTM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 Binary Counter 4 TM4BCH X03F65, R Compare register 4 TM4OCL lower 8 bitsBinary Counter 4 TM4BCL X03F64, R Binary counter 4 TM4BCH upper 8 bits Input Capture Register TM4ICL X03F66, R Input capture register TM4ICL lower 8 bitsTM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 TM2PWM Timer Mode RegistersTM2MD TM2EN TM3PWM Timer 3 mode register TM3MDTM3MD TM3EN IRQ0 IRQ1 IRQ2 TM4PWM Timer 4 mode register TM4MDTM4MD TM4EN TM5CK0 Timer 5 mode register TM5MDTM5MD TM5IR0 Timer Control Registers Watchdog timer control register Wdctr Remote control carrier output control register Rmctr Rmoen Chapter Serial Functions Serial Functions 1 Serial 0 Block Diagram Synchronous Serial Interface Serial Functions SC0BSY SBTSBO SBT SBO Serial Functions Start condition enabled Start condition disabled 1 Serial Data Input Edge and Output Edge serial interface Serial Interface Transfer TimingReceive Data Input Edge Transmit Data Output Edge SBI0 SBT0SBO0 Half-duplex Uart Serial Interface 1 Uart Transmission Timing Reception 2 Uart Reception Timing How to Use the Baud Rate Timer Serial Interface Control Registers SC0RXB SC0TRB Transmit/Receive Shift Registers, Receive Data BufferSerial interface 0 transmit/receive shift register SC0TRB SC0RXB SC0MD0 Serial Interface Mode RegistersSerial interface 0 mode register SC0MD0 SC0STE Serial interface 0 mode register 1 SC0MD1 SC0NPE Serial interface 0 mode register 2 SC0MD2SC0MD2 SC0BRKE Serial interface 0 mode register 3 SC0MD3 Serial Interface Control Register Serial interface 0 control register SC0CTR Chapter Conversion Functions AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANCTR0ANCTR1 ANBUF1 ANBUF0 A/D Conversion 1 A/D Conversion Timing 2 Recommended Circuit When Using A/D Conversion A/D Converter Control Registers 1 A/D Converter Control Registers D control register 0 ANCTR0 2 A/D Control Register AnctrAN0 D conversion control register 1 ANCTR1 ANCTR1 Anst 3 A/D Buffers Anbuf 5 4 3 2 1 Chapter AC Zero-Cross Circuit/Noise Filter 1 P21 Input Circuit Block Diagram AC Zero-Cross Circuit Operation 1 AC Line Waveform and IRQ Generation Timing 1 Noise Filtering Circuit Block Diagram Noise Filter Example Input and Output Waveforms for Noise Filter Sampling Input Waveform after noise filtering AC Zero-Cross Control Register Nfctr Nfctr Noise Filter Control Register NfctrNF0EN 128 Appendices8 Eprom Versions Appendices Appendices Tion start control,runaway Internal ROM final address data Characteristics of Eprom VersionOperating temperature There are no other functional differences Writing to Microcomputer with Internal Eprom Fit in the writing adapter and position the No.1 pin Vendor Data I/O Appendices Option Bit 2 Option bitAddress X07FFF Writing Adapter Connection Package Code SDIP042-P-0600 Package code QFP044-P-1010 Pin pitch 8mm 4 MN101CP117-BLBCEPROM Writing Adapter Connections Package code QFH048-P-0707 Pin pitch 5mm 5 MN101CP117-HP Eprom Writing Adapter connections Instruction Set 1101 111a #16 ∗1 d4 sign extended ∗2 d7 sign extended ∗3 d11 sign extended 0010 0011 0001 D11 0011 0100 0bp Ver2.01997.9.26 Instruction Map MN101C00 Series Instruction MAP Cbeq #8,abs16,d7/11 Cbne #8,abs16,d7/11 Summary of Special Function Registers Cpum P6IN7 P2PLU2 TM2BC4 TM2BC3 TM2BC2 TM2BC1 Nmicr Wdir TBLV0 Tbir MN101C115 Matsushita Electronics Corporation Sales Offices