Panasonic MN101C00 - page 87

■Pulse Added Type PWM Output Function

In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit

PWM output. Precise control is possible based on the number of PWM repetitions (256

times) to which this bit is appended. Settings for the pulse added type PWM output function

are listed below.

(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count

operation of timer 4.

(2) Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function

pin setting. Bit 4 of port 1 will be specified as the PWM output pin.

(3) Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the

clock source. The period of the output waveform is determined based on the clock source.

(4) Set the TM4PWM flag of the TM4MD register to "1" so that PWM operation is

selected.

(5) Set a value in the lower 8 bits of compare register 4 (TM4OCL). The high interval of

the output waveform is determined based on the value of the lower 8 bits of compare

register 4 (TM4OCL).

(6) Set the position of the added pulse in the upper 8 bits of compare register 4

(TM4OCH).

(7) Set the TM4EN flag of the TM4MD register to "1" to start the timer.

(8) When timer 4 begins operation, binary counter 4 will count upward from X'00'.

(9) A high-level signal is output from the port beginning when binary counter 4 starts

counting from X'00' and ending when the value of binary counter 4 matches the

value set in the TM4OCL register.

(10) When the value of binary counter 4 matches that of the TM4OCL register, a low-

level signal is output from the port.

(11) Binary counter 4 continues to count upward until X'FF' is reached. At the next count-

up cycle, the value of binary counter 4 is reset to X'00', and counting begins again.

A high-level signal is output from the port.

Figure 4-3-4 Pulse Added Type PWM Output

Chapter 4 Timer Functions

73

If bit 4 of port 1 is to be used as a

PWM output pin, set the P1DIR

and P1PLU registers.

PWM4 output is fixed at L with

X'FF' set at the lower 8

bits(TM40CL) of compare register.

Use of timer 4 at PWM mode

disables setting of X'FF' att

TM4OCL register.

Added pulse

: Added pulse

Basic PWM components

Repeated 256 times

Tn=X'00' Tn=X'01' Tn=X'02' Tn=X'03' Tn=X'04' Tn=X'FF'

Use a 16-bit access instruction to set the TM4OCH, TM4OCL

register.

16-bit Timer Operation (timer 4)

Contents

Main Page Page How to Read This Manual Manual Configuration Main text Summary Key information Supplementary information Finding Desired Information Related Manuals Where to Send Inquires Page Page Page Contents Chapter 1 Overview Chapter 2 Basic CPU Functions Chapter 3 Port Functions Chapter 4 Timer Functions Chapter 5 Serial Functions Chapter 6 A/D Conversion Functions Chapter 7 AC Zero-Cross Circuit/Noise Filter Appendices Page Page 1-1 Product Overview 1-1-1 Overview 1-1-2 Product Summary 1-2 Hardware Functions Page Page Page Page 1-3-2 Pin Function Summary Table 1-3-1 Pin Function Summary (2/4) Table 1-3-1 Pin Function Summary (3/4) 10 Table 1-3-1 Pin Function Summary (4/4) 12 1-4 Overview of Functions 1-4-1 Block Diagram Figure 1-4-1 Block Diagram of Functions) CPU MN101C00 1-5 Electrical Characteristics 1-5-1 Absolute Maximum Ratings Note: 1Applicable even for an interval of 100ms. F or more between a power source pin and GND to prevent from latchup. does not damage a chip, not guarantee the operation. 1-5-2 Operating Conditions to t c4: XI is the CPU clock Ta=40to +85C VDD=2.0 to 5.5V VSS=0V Note: *1. Only for 48-QFH package *2 Applicable only for 48-pin QFH package External clock input 1 OSC1 (OSC2 is unconnected) External clock input 2 XI (XO is unconnected)*2 Page 1-5-3 DC Characteristics 18 Input pin 1 MMOD to Input pin 2 P20, P22~P23 (Schmitt trigger input) Input pin 31 P21 (Schmitt trigger input) Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit to tfs V (Output) 20 I/O pin 5 P27 (RST) to I/O pin 6 P00 toP06, P10 to P14 (Schmitt trigger input) I/O pin 7 , P60 to P67 1-5-4 A/D Converter Characteristics to Ta=40 to+85C VDD=2.0 to 5.5V VSS=0V I/O pin 9 P80~P87 to 1-6 Option 1-6-1 ROM Option 22 Figure 1-6 ROM Option ( Address:X'7FFF' ) 1-6-2 Option Form 24 1-7 Outline Drawings Page 26 Page 28 2-1 Overview 2-2 Address Space 2-2-1 Memory Configuration 2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 2-3 Bus Interface 2-3-1 Overview 30 Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W 2-3-2 Control Registers 2-4 Interrupts 2-4-1 Accepting and Returning from Interrupts 32 2-4-2 Interrupt Sources and Vector Addresses * to X'04053'. Table 2-4-1 Interrupt Control Registers IRQ31CR cannot be used except for 48-pin QFH package. 2-4-3 Interrupt Control Registers n=0,1,2,3,4 34 Chapter 2 Basic CPU Functions Be sure to use the MIE flag of the PSW register to write to all interrupt control registers. Page 36 2-5 Reset Page 38 3-1 Overview Page 40 3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2) Name Address R/W Function Table 3-2-1 I/O Port Control Registers (2/2) 42 Name Address R/W Function Figure 3-2-1 Port Control Registers (1/2) 01245673 Figure 3-2-1 Port Control Registers (2/2) 44 01245673 3-2-2 I/O Port Control Registers 46 3-3 I/O Port Configuration and Functions P00,P02,P10 to P14 48 PA0 to PA7 Figure 3-3-3 Configuration and Functions of PA0 to PA7 50 P23 is only for 48-pin package. P21 Figure 3-3-5 Configuration and Functions of P21 52 P27 Figure 3-3-6 Configuration and Functions of P27 P7PLUD0 P7DIR0 P7OUT0 P7IN0 P7PLUD1 P7DIR1 P7IN1 P7OUT1 54 P60 to P67,P80 to P87 Figure 3-3-9 Configuration and Functions of P80 to P87 Figure 3-3-8 Configuration and Functions of P60 to P67 Page 56 4-1 Overview Figure 4-1-1 Timers 2, 3 Block Diagram 58 Figure 4-1-2 Timer 4 Block Diagram Figure 4-1-3 Timer 5/Time Base Block Diagram 60 Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram Figure 4-1-5 Remote Control Transmission Block Diagram 4-2 8-bit Timer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions 4-2-2 Operation 64 Page Page Page Page 4-3 16-bit Timer Operation (timer 4) 4-3-1 Overview 4-3-2 Operation Page Page Page Page 74 Page 76 4-4 8-bit Timer Operation (timer 5) 4-4-1 Overview 4-4-2 Operation 4-5 Time Base Operation 4-5-1 Overview 4-5-2 Operation 4-6 Watchdog Timer Operation 4-6-1 Overview 4-6-2 Setup and Operation 4-7 Remote Control Output Operation 4-7-1 Overview 4-7-2 Setup and Operation 80 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation 4-9 Timer Function Control Registers 4-9-1 Overview Function 19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers R/W: Readable and writable R: Read only 4-9-2 Programmable Timer/Counters Page 84 4-9-3 Timer Mode Registers Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W) (2) Timer 3 mode register (TM3MD) Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W) 86 (3) Timer 4 mode register (TM4MD) Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W) (4) Timer 5 mode register (TM5MD) * 48QFH package only Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W) 88 4-9-4 Timer Control Registers (1) Watchdog timer control register (WDCTR) (at reset: -------0) WDEN Timer Function Control Registers 90 Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W) Page 92 5-1 Overview Figure 5-1-1 Serial 0 Block Diagram 5-2 Synchronous Serial Interface 5-2-1 Overview 5-2-2 Setup and Operation Page Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge) Page Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) Figure 5-2-4 Synchronous Serial Interface Reception Timing (reception at falling edge) SC0LNG2 to 0 012345670 Synchronous Serial Interface 5-2-3 Serial Interface Transfer Timing Page 5-3 Half-duplex UART Serial Interface 5-3-1 Overview 5-3-2 Setup and Operation Page Page Figure 5-3-2 UART Reception Timing Half-duplex UART Serial Interface 5-3-3 How to Use the Baud Rate Timer Transfer Speed 4.0 fosc (MHz) (bps) 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface. See table 5-4-1. Table 5-4-1 Serial Interface Registers 5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W) (2) Serial interface 0 mode register 1 (SC0MD1) Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W) 110 (3) Serial interface 0 mode register 2 (SC0MD2) Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W) (4) Serial interface 0 mode register 3 (SC0MD3) Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W) 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) Page 114 6-1 Overview Figure 6-1-1 A/D Converter Block Diagram 6-2 A/D Conversion 116 6-3 A/D Converter Control Registers 6-3-1 Overview 118 6-3-2 A/D Control Register (ANCTR) Figure 6-3-1 A/D Control Register 0 (ANCTR0: X'03F90', R/W) This readable and writable 8-bit register controls the operation of the A/D converter. (1) A/D control register 0 (ANCTR0) (2) A/D conversion control register 1 (ANCTR1) Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) 120 6-3-3 A/D Buffers (ANBUF) Page Chapter 7 AC Zero-Cross Circuit/Noise Filter 122 7-1 Overview Figure 7-1-1 P21 Input Circuit Block Diagram 7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-3 Noise Filter Noise Filter 7-3-1 Overview fs/2 Figure 7-3-1 Noise Filtering Circuit Block Diagram 7-3-2 Example Input and Output Waveforms for Noise Filter 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit. Table 7-4-1 AC Zero-Cross Control Register 7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter. Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W) Page Page 8-1 EPROM Versions 8-1-1 Overview 8-1-2 Cautions on Use 8-1-3 Erasing Written Data in Windowed Packages (PX-AP101C11-SDC, PX-AP101C11-FBC) 8-1-4 Characteristics of EPROM Version 8-1-5 Writing to Microcomputer with Internal EPROM Fit in the writing adapter and position the No.1 pin. Figure 8-1-1 Mount on the writing adapter and position of No.1 pin. Page 8-1-6 Cautions on Operating the ROM Writer 8-1-7 Option Bit Page Page Page 8-2 Instruction Set 1010DnDm 1 d8 sign extended 2 d4 zero extended 3 d8 zero extended 4A=An, a=Am 5 #8 sign extended 6 #8 zero extended 142 1101 111a <#16 .... .... ...> 9 mn <#8. ...> 1D=DWn, d=DWm 2 A=An, a=Am 3d=DWm 4D=DWk 1 d4 sign extended 2 d7 sign extended 3 d11 sign extended 144 1 d4 sign extended 2 d7 sign extended 3 d11 sign extended 2 d11 sign extended 4 d16 sign extended 5 aa=abs18.17 16 1 d7 sign extended 3 d12 sign extended Page Page Page Page Page Page Page Page Page Page Semiconductor Company Matsushita Electronics Corporation CANADA SALES OFFICE GERMANY SALES OFFICE U.K. SALES OFFICE SALES OFFICES HONG KONG SALES OFFICE TAIWAN SALES OFFICE SINGAPORE SALES OFFICE MALAYSIA SALES OFFICE