Chapter 2 Basic CPU Functions

2-3 Bus Interface

2-3-1 Overview

The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode.

2-3-2 Control Registers

The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone.

MEMCTR

(1) Memory control register(MEMCTR)

7

6

 

5

 

4

 

3

 

2

 

1

0

 

 

IOW1

IOW0

IVBA

 

 

 

 

 

 

IRWE

 

 

 

 

(at reset: 11001011)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Must be set to 11.

 

 

 

 

 

 

 

 

 

IRWE

 

Set software write for interrupt request flag

 

 

 

 

 

 

 

Software write disable

0

 

Even if data is written to each interrupt control

 

register (xxxICR), the state of the interrupt

 

 

 

 

 

 

request flag (xxxIR) will not change.

1

 

Software write enable

 

 

 

 

 

 

 

 

 

Must be set to 1.

 

 

 

 

 

 

 

 

Must be set to 0

 

 

 

 

 

 

 

 

 

IVBA

 

Base address setting for interrupt vector table

0Interrupt vector base = X'04000'

1Interrupt vector base = X'00100'

IOW1 to 0

Number of wait cycles set when

Bus cycle at

 

accessing special register area

20MHz oscillation

00

No wait cycles

100ns

 

 

 

01

1 wait cycle

150ns

 

 

 

10

2 wait cycles

200ns

 

 

 

11

3 wait cycles

250ns

 

 

 

Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W

30 Bus Interface

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Panasonic MN101C00 user manual Bus Interface, Control Registers, Memory control registerMEMCTR, Memctr, IOW1 IOW0 Ivba Irwe