Quatech ES-100 user manual Interrupt Enable Register, Interrupt Identification Register

INTERRUPT ENABLE REGISTER

This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.

BIT	DESCRIPTION
7	0 --- reserved
6	0 --- reserved
5	0 --- reserved
4	0 --- reserved
3	EDSSI --- MODEM Status Interrupt:
	When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and
	data carrier detect.
2	ELSI --- Receiver Line Status Interrupt:
	When set (logic 1), enables interrupt on overrun, parity, framing errors, and break
	indication.
1	ETBEI --- Transmitter Holding Register Empty Interrupt:
	When set (logic 1), enables interrupt on transmitter holding register empty.
0	ETBEI --- Received Data Available Interrupt:
	When set (logic 1), enables interrupt on received data available. For 16550 FIFO
	mode, interrupts are also enabled for receive FIFO trigger level reached and for receive
	timeout.
	Figure 14 --- Interrupt Enable Register bit definitions

INTERRUPT IDENTIFICATION REGISTER

This read-only register is located at I/O address [base+2]. When this register is read, the UART freezes all interrupts and indicates the highest priority interrupt. During this time, new interrupts are detected by the UART, but are not reported in this register until the access completes.

For the 16550 only, this register can be used to indicate whether the FIFO mode is engaged by examining bits 6 and 7.

14 Quatech ES-100D User's Manual